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The past few years have seen a significant increase in sensing applications in the 60 GHz band (an unlicensed band open for a wide variety of applications). This is primarily due to advances in mmWave technology that have reduced the size, cost and power consumption of these sensing devices. Typical applications include:
The smaller wavelength of approximately 5 mm for 60 GHz signals directly translates to higher velocity resolution and small form factor. Many sensing applications that earlier operated at lower frequency bands (3-10 GHz) are now moving to 60 GHz to leverage these advantages.
While mmWave radar has been traditionally employed in target detection and tracking, there has been a trend toward using radar signals for target classification [3]. Many of these classification algorithms use Machine Learning (ML) to leverage the radar’s high sensitivity to motion. The examples include: motion classification for reducing false alarms in building automation, fall detection for elderly care, and gesture recognition.
TI’s integrated radar-on-chip devices, such as IWRL6432 [1], are designed for the above applications. IWRL6432 has an integrated RF front end and a Hardware Accelerator (HWA@80 MHz) optimized for radar signal processing. The on-chip MCU, Arm® Cortex®-M4F (@160 MHz), provides sufficient computational capability for post-processing algorithms such as tracking and classification. The device is designed with various low-power modes to support applications where minimizing power consumption is critical.
Figure 2-1 depicts the typical processing flow of an algorithmic chain that incorporates an ML-based classifier. First basic physical layer processing is done on the raw ADC data received from the radar front end. This block involves a series of FFTs to separate the signal based on range, Doppler, and angle of arrival [2]. In some cases (e.g. Case-Study-1: Motion Classification), this can additionally be followed by detection and tracking algorithms.
The next step involves feature extraction, where the output of the previous block is processed to provide input to an ML-based classifier. The choice of feature extraction and the corresponding classifier that follows are closely coupled. Some popular options found in the literature [3] are listed below:
There is a tradeoff between the intelligence in the feature extraction block and the complexity of the classifier. Approach (3) typically results in the lighter-weight classifier. The selection of the feature extraction block and the classifier architecture depends on the complexity of the classification task as well as requirements such as classifier performance, frame rate, and available memory and computing power.
In a typical implementation on the IWRL6432, the radar physical layer (PHY) processing is handled by the HWA while the classifier runs on the MCU (M4F). Hand-crafted feature extraction typically runs on the M4F with some assistance from the HWA.