SWRA794A June   2024  – September 2024 AWRL1432 , AWRL6432 , IWRL1432 , IWRL6432 , IWRL6432AOP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Acronyms Used in This Document
  5. 2 Introduction
  6. 3 Purpose of Calibrations
  7. 4 Typical Stages of Calibration
    1. 4.1 Factory Calibrations
    2. 4.2 APLL Calibration
    3. 4.3 Runtime Calibrations
  8. 5 List and Description of Calibrations
    1. 5.1 APLL Hardware Calibration
    2. 5.2 Synthesizer VCO Calibration
    3. 5.3 LO Distribution Calibration
    4. 5.4 Power Detector Calibration
    5. 5.5 TX Power Calibration
    6. 5.6 RX Gain Calibration
  9. 6 Software configurability of Calibrations
    1. 6.1 Software Sequence for Factory Calibrations
      1. 6.1.1 mmWaveLink Initialization
      2. 6.1.2 FECSS Power-On
      3. 6.1.3 APLL Power-On and Hardware Calibration
      4. 6.1.4 RF Channel Configuration
      5. 6.1.5 Trigger Factory Calibrations
      6. 6.1.6 Factory Calibration Data Store
      7. 6.1.7 APLL Power-Off
      8. 6.1.8 FECSS Power-Off
      9. 6.1.9 mmWaveLink De-Initialization
    2. 6.2 Software Sequence for Runtime (In-Field) Operation
      1. 6.2.1 Initialization
        1. 6.2.1.1 mmWaveLink Initialization
        2. 6.2.1.2 FECSS Power-On
        3. 6.2.1.3 APLL Power-On and Hardware Calibration
        4. 6.2.1.4 Factory Calibration Data Restore
        5. 6.2.1.5 Temperature Sensor Configuration
      2. 6.2.2 Profile Configuration
        1. 6.2.2.1 Profile Common Configuration
        2. 6.2.2.2 Profile Time Configuration
        3. 6.2.2.3 Frame Configuration
      3. 6.2.3 Runtime Calibration
        1. 6.2.3.1 Temperature Sensor Trigger
        2. 6.2.3.2 Runtime Calibration Configure and Trigger
        3. 6.2.3.3 Tx CLPC Calibration
      4. 6.2.4 Frame Trigger
        1. 6.2.4.1 Sensor Start
        2. 6.2.4.2 Sensor Status
        3. 6.2.4.3 Sensor Stop
      5. 6.2.5 Deep Sleep Entry and Exit
      6. 6.2.6 De-Initialization
  10. 7  Recommended Calibration Sequence: OLPC vs CLPC
    1. 7.1 Safety Application With OLPC Tx Power Cal
    2. 7.2 Non-Safety Application With OLPC Tx Power Cal
    3. 7.3 Application With CLPC Tx Power Cal
  11. 8 Summary
  12. 9 References
  13. 10Revision History

6.2.5 Deep Sleep Entry and Exit

Once all the functional chirps are transmitted, the rl_fecssDevClockCtrl API can be used to power-off the APLL while entering deep sleep. The rl_fecssDevPwrOff API can be used for power down the FECSS. FECSS power down must be done with retaining the memory.

After successfully entering deep sleep and while exiting deep sleep, the rl_fecssDevPwrOn can be used to power up the FECSS. FECSS powerup must be done in warm boot mode. The configuration structure of the rl_fecssDevClockCtrl API has a sub field, c_ApllClkCtrl, that can be used to powerup the APLL. APLL hardware calibration is not needed during the warm boot or after exiting deep sleep.