SWRA797 September   2024 CC1312PSIP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 RF Function and Frequency Range
    2. 1.2 LP-EM-CC1312PSIP
  5. 2Software – Certified PHYs
    1. 2.1 14dBm Tx and Rx Port
      1. 2.1.1 WB-DSSS
      2. 2.1.2 TI 15.4
      3. 2.1.3 PowerG PHY
      4. 2.1.4 mioty PHY
      5. 2.1.5 WiSun PHY
    2. 2.2 20dBm Tx Port
      1. 2.2.1 WB-DSSS PHY
      2. 2.2.2 TI 15.4 PHY
      3. 2.2.3 PowerG PHY
      4. 2.2.4 mioty PHY
      5. 2.2.5 Wi-SUN PHY
  6. 3Hardware
    1. 3.1 Recommended Layout
      1. 3.1.1 4-Layer Design
      2. 3.1.2 2-Layer Design
      3. 3.1.3 GND Vias
      4. 3.1.4 Maximum Track Length
    2. 3.2 Antennas
      1. 3.2.1 Certified Antennas
      2. 3.2.2 Cross-Linking Certified Antennas
    3. 3.3 Reusing of FCC ID and IC
      1. 3.3.1 Documentation Supplied to the TCB
      2. 3.3.2 Permissive Change Policy
        1. 3.3.2.1 Class 1 Permissive Change (C1PC)
        2. 3.3.2.2 Class 2 Permissive Change (C2PC)
        3. 3.3.2.3 Class 3 Permissive Change (C3PC)
      3. 3.3.3 Changes in the FCC ID or IC
      4. 3.3.4 Re-use of FCC ID and IC Certifications Step-by-Step
    4. 3.4 Recommended Production Testing
  7. 4References

3.1.1 4-Layer Design

The LP-EM-CC1312PSIP [4.2] is available for evaluation of the CC1312PSIP [4.1] and is a 4-layer design. The function of the LP-EM-CC1312PSIP [4.2] has been shown in Figure 1-3. This is the design that has been tested at FCC test house. LP-EM-CC1312PSIP [4.2] has also been tested at 868MHz to sell the evaluation board in Europe.

The 4-layer layout has been designed to minimize the emissions from the board. The top layer is the component layer which the CC1312PSIP [4.1] is soldered and assembled, refer to Figure 3-1. Directly underneath the top layer, is the second layer that is mostly the GND layer, refer to Figure 3-2. The third layer is the layer where the majority of the routing is performed, refer to Figure 3-3. The bottom layer there is minimum routing and the majority of this layer is a GND plane, refer to Figure 3-4.

By enclosing the majority of the routing on the third layer, between the GND on the second and fourth layers. The GND layers with the GND vias then form a Faraday cage effect on the majority of the routing performed on the third layer which helps to minimize unwanted emissions from the routing of the signals from the CC1312PSIP [4.1]. As can be seen in Figure 3-1 and Figure 3-4, the routing on the top and bottom layers are kept to a minimum.

A 4-layer design is the preferred choice for a robust and low emission design.

Top Component Layer of the 4-Layer PCB DesignFigure 3-1 Top Component Layer of the 4-Layer PCB Design
Second Layer of the 4-Layer PCB DesignFigure 3-2 Second Layer of the 4-Layer PCB Design
Third Layer of the 4-Layer PCB DesignFigure 3-3 Third Layer of the 4-Layer PCB Design
Bottom Layer of the 4-Layer PCB DesignFigure 3-4 Bottom Layer of the 4-Layer PCB Design