SWRA797 September   2024 CC1312PSIP

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 RF Function and Frequency Range
    2. 1.2 LP-EM-CC1312PSIP
  5. 2Software – Certified PHYs
    1. 2.1 14dBm Tx and Rx Port
      1. 2.1.1 WB-DSSS
      2. 2.1.2 TI 15.4
      3. 2.1.3 PowerG PHY
      4. 2.1.4 mioty PHY
      5. 2.1.5 WiSun PHY
    2. 2.2 20dBm Tx Port
      1. 2.2.1 WB-DSSS PHY
      2. 2.2.2 TI 15.4 PHY
      3. 2.2.3 PowerG PHY
      4. 2.2.4 mioty PHY
      5. 2.2.5 Wi-SUN PHY
  6. 3Hardware
    1. 3.1 Recommended Layout
      1. 3.1.1 4-Layer Design
      2. 3.1.2 2-Layer Design
      3. 3.1.3 GND Vias
      4. 3.1.4 Maximum Track Length
    2. 3.2 Antennas
      1. 3.2.1 Certified Antennas
      2. 3.2.2 Cross-Linking Certified Antennas
    3. 3.3 Reusing of FCC ID and IC
      1. 3.3.1 Documentation Supplied to the TCB
      2. 3.3.2 Permissive Change Policy
        1. 3.3.2.1 Class 1 Permissive Change (C1PC)
        2. 3.3.2.2 Class 2 Permissive Change (C2PC)
        3. 3.3.2.3 Class 3 Permissive Change (C3PC)
      3. 3.3.3 Changes in the FCC ID or IC
      4. 3.3.4 Re-use of FCC ID and IC Certifications Step-by-Step
    4. 3.4 Recommended Production Testing
  7. 4References

3.1.2 2-Layer Design

Since the CC1312PSIP [4.1] has integrated all the components inside the package. The routing requirements to the CC1312PSIP are simplified and this opens up the option to produce a 2-layer PCB design instead of a 4-layer PCB design to save PCB costs.

Since there is only 2 layers of the PCB, the more IO routing inherently decreases the amount of GND on the PCB. Not only does the GND plane reduce, but the Faraday cage effects are also reduced compared to a 4-layer design.

Figure 3-5 shows the top layer of a 2-layer PCB design and Figure 3-6 shows the bottom layer of the 2-layer PCB design. The Faraday cage concept is still tried to be maintained despite having just two layers. Making a 2-layer design is more challenging than making a 4-layer design since the design has greater requirements that a good RF layout concept must be followed. If good RF layout practice is not followed on the end-product, then the unintentional radiated emissions increase which can cause failures at the certified test lab when proving the level of unintentional radiators is within the regulatory limits.

The top layer shown in Figure 3-5 is the component layer with the main routing layer. The bottom layer shown in Figure 3-6 is for minor routing and mostly GND plane layer. The bottom layer which is mostly a GND layer is important for the Faraday cage effects and also to maintain a large GND plane as possible for the antenna.

A smaller GND plane naturally gives a lower antenna efficiency and a smaller bandwidth. This is one of the reasons why there must be as little as possible routing on this layer to maintain a highly efficient antenna for a GND plane size that is much smaller than a quarter-wave. The quarter-wave at 915MHz is 8.2cm so GND planes that are less than this distance have a reduced efficiency and bandwidth. The antenna must see as large as possible GND plane for best antenna efficiency. If the GND plane is effectively divided up due to routing, the antenna efficiency is lower.

Figure 3-7 shows the top and bottom layer of the 2-layer PCB design directly underneath the CC1312PSIP. The GND vias and the distance between the GND vias are essential to maintain a good Faraday cage effect whilst just having a 2-layer design.

Note: Directly underneath the CC1312PSIP on the bottom layer, there must be GND to attenuate any unwanted radiation. The majority of the routing on the top layer, must be covered by GND directly underneath on the bottom layer. This creates a Faraday cage effect whilst just using a 2-layer design. This is important to follow otherwise the radiated emissions increase.

Making a 2-layer design requires more caution in the RF layout stage of the design. By not having a good GND plane or using enough GND vias, then the design has increased emissions. If there is uncertainty or if the previous guidelines cannot be followed, then a 4-layer design can be used.

Top Layer of 2-Layer PCB DesignFigure 3-5 Top Layer of 2-Layer PCB Design
Bottom Layer of 2-layer PCB DesignFigure 3-6 Bottom Layer of 2-layer PCB Design
Top and Bottom Layer of 2-Layer PCB Directly Underneath the CC1312PSIP Figure 3-7 Top and Bottom Layer of 2-Layer PCB Directly Underneath the CC1312PSIP