SWRS188D May   2017  – December 2021 AWR1243

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagram
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
      1. 7.2.1 Signal Descriptions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Power-On Hours (POH)
    4. 8.4 Recommended Operating Conditions
    5. 8.5 Power Supply Specifications
    6. 8.6 Power Consumption Summary
    7. 8.7 RF Specification
    8. 8.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 8.9 Timing and Switching Characteristics
      1. 8.9.1 Power Supply Sequencing and Reset Timing
      2. 8.9.2 Synchronized Frame Triggering
      3. 8.9.3 Input Clocks and Oscillators
        1. 8.9.3.1 Clock Specifications
      4. 8.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.9.4.1 Peripheral Description
          1. 8.9.4.1.1 SPI Timing Conditions
          2. 8.9.4.1.2 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          3. 8.9.4.1.3 SPI Peripheral Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        2. 8.9.4.2 Typical Interface Protocol Diagram (Peripheral Mode)
      5. 8.9.5 LVDS Interface Configuration
        1. 8.9.5.1 LVDS Interface Timings
      6. 8.9.6 General-Purpose Input/Output
        1. 8.9.6.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 8.9.7 Camera Serial Interface (CSI)
        1. 8.9.7.1 CSI Switching Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
        1. 9.3.1.1 Clock Subsystem
        2. 9.3.1.2 Transmit Subsystem
        3. 9.3.1.3 Receive Subsystem
      2. 9.3.2 Host Interface
    4. 9.4 Other Subsystems
      1. 9.4.1 ADC Data Format Over CSI2 Interface
  10. 10Monitoring and Diagnostics
    1. 10.1 Monitoring and Diagnostic Mechanisms
  11. 11Applications, Implementation, and Layout
    1. 11.1 Application Information
    2. 11.2 Short-, Medium-, and Long-Range Radar
    3. 11.3 Reference Schematic
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2. 13.2 Tray Information for

5 Revision History

Changes from May 1, 2020 to December 8, 2021 (from Revision C (May 2020) to Revision D (December 2021))

  • Section 1 (Features): Updated/Changed the RX noise figure value from "14" to "12" dbGo
  • (Features): Updated/Changed the Phase noise at 1-MHz value from "–92 " to "–93" dBc/HzGo
  • Global: Updated to reflect Functional Safety-Compliance and relevant certification collateralGo
  • Global: Replaced "A2D" with "ADC"; Changed Masters Subsystem and Masters R4F to Main Subsystem and Main R4F; Shift to more inclusive langauge made in terms of Master/Slave terminologyGo
  • (Features) : Mentioned the specific operating temperature range for the mmWave SensorGo
  • (Applications) :Revised the figure and updated application linksGo
  • (Device Information): Removed a pre-production orderable part number (XA1243FPBGABL) from the table and its assosiated features. Go
  • Updated/Changed Functional Block Diagram to remove XA1243FPBGABL OPN specific features.Go
  • (Device Comparison) : Removed a row on Functionaly-Safety compliance and instead added a table-note for this and LVDS Interface; modified the existing table-note on simultaneous TX operation; Additional information on Device security added.Go
  • (Device Comparison) : Updated/Changed RF Specification Receiver from "Max real sampling rate (Msps)" to "Max real/complex 2x sampling rate (Msps)"; and "Max complex sampling rate (Msps)" to "Max complex 1x sampling rate (Msps)"Go
  • Section 7.2.1 (Signal Descriptions): Updated/Changed the default pull from "Open Drain" to " —"Go
  • (Signal Descriptions): Removed XA1243FPBGABL OPN specific pin functions; updated descriptions for CLKP and CLKM pins for Reference OscillatorGo
  • (Absolute Maximum Ratings): Added entries for externally supplied power on the RF inputs (TX and RX) and a table-note for the signal level applied on TX.Go
  • (Power Supply Specifications): Updated/Changed footnote in Table 8-1 Go
  • (Maximum Current Rating at Power Terminals): Updated footnotes section to add estimation assumption for VIOIN railGo
  • (Average Power Consumption at Power Terminals): Removed 3TX, 4RX power numbers since only 2TX are operational simultaneously in the deviceGo
  • (RF Specification): Updated/Changed RF Specification Receiver from "A2D sampling rate (complex)" to "ADC sampling rate (complex 1x)"; and "A2D sampling rate (real)" to "ADC sampling rate (real/complex 2x)"Go
  • (RF Specification): Updated/Changed the table to remove XA1243FPBGABL specific featuresGo
  • (Synchronized Frame Triggering): Updated the maximum pulse width to 4nsGo
  • (Clock Specifications): Updated/Changed Table 8-6 to reflect correct device operating temperature range.Go
  • (Table. External Clock Mode Specifications): Revised frequency tolerance specs from +/-50 to +/-100 ppmGo
  • (Switching Characteristics for Output Timing versus Load Capacitance): Updated/Modified the table to remove Slew Rate = 1 condition; removed a footnoteGo
  • Figure 9-1: Updated the figure to remove XA1243FPBGABL OPN specific features. Go
  • Transmit Subsystem (Per Channel): Removed the mention of AWR1243P altogether and hence programmable phase shifters as well.Go
  • (Monitoring and Diagnostic Mechanisms): Added a new sectionGo
  • (Reference Schematics) : Added weblinks to AWR1243 EVM documentation collateral Go
  • (Device Nomenclature):Updated/changed Device Nomenclature Go