SWRS188D
May 2017 – December 2021
AWR1243
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Functional Block Diagram
5
Revision History
6
Device Comparison
6.1
Related Products
7
Terminal Configuration and Functions
7.1
Pin Diagram
7.2
Signal Descriptions
7.2.1
Signal Descriptions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Power-On Hours (POH)
8.4
Recommended Operating Conditions
8.5
Power Supply Specifications
8.6
Power Consumption Summary
8.7
RF Specification
8.8
Thermal Resistance Characteristics for FCBGA Package [ABL0161]
8.9
Timing and Switching Characteristics
8.9.1
Power Supply Sequencing and Reset Timing
8.9.2
Synchronized Frame Triggering
8.9.3
Input Clocks and Oscillators
8.9.3.1
Clock Specifications
8.9.4
Multibuffered / Standard Serial Peripheral Interface (MibSPI)
8.9.4.1
Peripheral Description
8.9.4.1.1
SPI Timing Conditions
8.9.4.1.2
SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
8.9.4.1.3
SPI Peripheral Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
8.9.4.2
Typical Interface Protocol Diagram (Peripheral Mode)
8.9.5
LVDS Interface Configuration
8.9.5.1
LVDS Interface Timings
8.9.6
General-Purpose Input/Output
8.9.6.1
Switching Characteristics for Output Timing versus Load Capacitance (CL)
8.9.7
Camera Serial Interface (CSI)
8.9.7.1
CSI Switching Characteristics
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Subsystems
9.3.1
RF and Analog Subsystem
9.3.1.1
Clock Subsystem
9.3.1.2
Transmit Subsystem
9.3.1.3
Receive Subsystem
9.3.2
Host Interface
9.4
Other Subsystems
9.4.1
ADC Data Format Over CSI2 Interface
10
Monitoring and Diagnostics
10.1
Monitoring and Diagnostic Mechanisms
11
Applications, Implementation, and Layout
11.1
Application Information
11.2
Short-, Medium-, and Long-Range Radar
11.3
Reference Schematic
12
Device and Documentation Support
12.1
Device Nomenclature
12.2
Tools and Software
12.3
Documentation Support
12.4
Support Resources
12.5
Trademarks
12.6
Electrostatic Discharge Caution
12.7
Glossary
13
Mechanical, Packaging, and Orderable Information
13.1
Packaging Information
13.2
Tray Information for
1
Features
FMCW transceiver
Integrated PLL, transmitter, receiver, Baseband, and ADC
76- to 81-GHz coverage with 4 GHz available bandwidth
Four receive channels
Three transmit channels (two can be used simultaneously)
Ultra-accurate chirp engine based on fractional-N PLL
TX power: 12 dBm
RX noise figure:
14 dB (76 to 77 GHz)
15 dB (77 to 81 GHz)
Phase noise at 1 MHz:
–95 dBc/Hz (76 to 77 GHz)
–93 dBc/Hz (77 to 81 GHz)
Built-in calibration and self-test
Built-in firmware (ROM)
Self-calibrating system across process and temperature
Host interface
Control interface with external processor over SPI
Data interface with external processor over MIPI D-PHY and CSI2 V1.1
Interrupts for fault reporting
Functional Safety-Compliant
Developed for functional safety applications
Documentation available to aid ISO 26262 functional safety system design up to ASIL-D
Hardware integrity up to ASIL-B
Safety-related certification
ISO 26262 certified upto ASIL B by TUV SUD
AEC-Q100 qualified
Device advanced features
Embedded self-monitoring with no host processor involvement
Complex baseband architecture
Embedded interference detection capability
Power management
Built-in LDO network for enhanced PSRR
I/Os support dual voltage 3.3 V/1.8 V
Clock source
Supports externally driven clock (square/sine) at 40 MHz
Supports 40 MHz crystal connection with load capacitors
Easy hardware design
0.65-mm pitch, 161-pin 10.4 mm × 10.4 mm flip chip BGA package for easy assembly and low-cost PCB design
Small solution size
Operating Conditions
Junction temp range: –40°C to 125°C