SWRS195C October   2019  – April 2024 CC2652P

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagram—RGZ Package (Top View)
    2. 6.2 Signal Descriptions—RGZ Package
    3. 6.3 Connections for Unused Pins and Modules
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Power Supply and Modules
    5. 7.5  Power Consumption—Power Modes
    6. 7.6  Power Consumption—Radio Modes
    7. 7.7  Nonvolatile (Flash) Memory Characteristics
    8. 7.8  Thermal Resistance Characteristics
    9. 7.9  RF Frequency Bands
    10. 7.10 Bluetooth Low Energy—Receive (RX)
    11. 7.11 Bluetooth Low Energy—Transmit (TX)
    12. 7.12 Zigbee and Thread—IEEE 802.15.4-2006 2.4GHz (OQPSK DSSS1:8, 250kbps): RX
    13. 7.13 Zigbee and Thread—IEEE 802.15.4-2006 2.4GHz (OQPSK DSSS1:8, 250kbps): TX
    14. 7.14 Timing and Switching Characteristics
      1. 7.14.1 Reset Timing
      2. 7.14.2 Wakeup Timing
      3. 7.14.3 Clock Specifications
        1. 7.14.3.1 48MHz Crystal Oscillator (XOSC_HF)
        2. 7.14.3.2 48MHz RC Oscillator (RCOSC_HF)
        3. 7.14.3.3 2MHz RC Oscillator (RCOSC_MF)
        4. 7.14.3.4 32.768kHz Crystal Oscillator (XOSC_LF)
        5. 7.14.3.5 32kHz RC Oscillator (RCOSC_LF)
      4. 7.14.4 Synchronous Serial Interface (SSI) Characteristics
        1. 7.14.4.1 Synchronous Serial Interface (SSI) Characteristics
        2.       36
      5. 7.14.5 UART
        1. 7.14.5.1 UART Characteristics
    15. 7.15 Peripheral Characteristics
      1. 7.15.1 ADC
        1. 7.15.1.1 Analog-to-Digital Converter (ADC) Characteristics
      2. 7.15.2 DAC
        1. 7.15.2.1 Digital-to-Analog Converter (DAC) Characteristics
      3. 7.15.3 Temperature and Battery Monitor
        1. 7.15.3.1 Temperature Sensor
        2. 7.15.3.2 Battery Monitor
      4. 7.15.4 Comparators
        1. 7.15.4.1 Low-Power Clocked Comparator
        2. 7.15.4.2 Continuous Time Comparator
      5. 7.15.5 Current Source
        1. 7.15.5.1 Programmable Current Source
      6. 7.15.6 GPIO
        1. 7.15.6.1 GPIO DC Characteristics
    16. 7.16 Typical Characteristics
      1. 7.16.1 MCU Current
      2. 7.16.2 RX Current
      3. 7.16.3 TX Current
      4. 7.16.4 RX Performance
      5. 7.16.5 TX Performance
      6. 7.16.6 ADC Performance
  9. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  System CPU
    3. 8.3  Radio (RF Core)
      1. 8.3.1 Bluetooth 5.2 Low Energy
      2. 8.3.2 802.15.4 (Thread, Zigbee, 6LoWPAN)
    4. 8.4  Memory
    5. 8.5  Sensor Controller
    6. 8.6  Cryptography
    7. 8.7  Timers
    8. 8.8  Serial Peripherals and I/O
    9. 8.9  Battery and Temperature Monitor
    10. 8.10 µDMA
    11. 8.11 Debug
    12. 8.12 Power Management
    13. 8.13 Clock Systems
    14. 8.14 Network Processor
  10. 9 Application, Implementation, and Layout
    1. 9.1 Reference Designs
  11. 10Device and Documentation Support
    1. 10.1 Tools and Software
      1. 10.1.1 SimpleLink™ Microcontroller Platform
    2. 10.2 Documentation Support
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

7.13 Zigbee and Thread—IEEE 802.15.4-2006 2.4GHz (OQPSK DSSS1:8, 250kbps): TX

Measured on the CC1352PEM-XD7793-XD24-PA24 reference design with Tc = 25°C, VDDS = 3.0V, fRF= 2440MHz with
DC/DC enabled and high power PA connected to VDDS unless otherwise noted.
All measurements are performed at the antenna input with a combined RX and TX path, except for high power PA which is measured at a dedicated antenna connection. All measurements are performed conducted.
 
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
General Parameters
Max output power, high power PA Differential mode, delivered to a single-ended 50Ω load through a balun 19.5 dBm
Output power programmable range,
high power PA		 Differential mode, delivered to a single-ended 50Ω load through a balun 6 dB
Max output power, high power PA, 10dBm configuration(5) Differential mode, delivered to a single-ended 50Ω load through a balun 10.5 dBm
Output power programmable range,
high power PA, 10dBm configuration(5)		 Differential mode, delivered to a single-ended 50Ω load through a balun 5 dB
Max output power, regular PA Differential mode, delivered to a single-ended 50Ω load through a balun 5 dBm
Output power programmable range,
regular PA		 Differential mode, delivered to a single-ended 50Ω load through a balun 26 dB
Spurious emissions and harmonics
Spurious emissions,
high-power PA(1)(3)		 f < 1GHz, outside restricted bands +20dBm setting < –39 dBm
f < 1GHz, restricted bands FCC < –49 dBm
f > 1GHz, including harmonics –40 dBm
Harmonics,
high-power PA(1)(4)		 Second harmonic –35 dBm
Third harmonic –42 dBm
Spurious emissions,
high-power PA, 10dBm configuration(1)(3)(5)		 f < 1GHz, outside restricted bands +10dBm setting(5) < –36 dBm
f < 1GHz, restricted bands ETSI < –47 dBm
f < 1GHz, restricted bands FCC < –55 dBm
f > 1GHz, including harmonics –42 dBm
Harmonics,
high-power PA, 10dBm configuration(1)(5)		 Second harmonic < –42 dBm
Third harmonic < –42 dBm
Spurious emissions,
regular PA(1)(2)		 f < 1GHz, outside restricted bands +5dBm setting < –36 dBm
f < 1GHz, restricted bands ETSI < –47 dBm
f < 1GHz, restricted bands FCC < –55 dBm
f > 1GHz, including harmonics < –42 dBm
Harmonics,
regular PA(1)		 Second harmonic < –42 dBm
Third harmonic < –42 dBm
IEEE 802.15.4-2006 2.4GHz (OQPSK DSSS1:8, 250kbps)
Error vector magnitude,
high power PA		 +20dBm setting 2%
Error vector magnitude,
high power PA, 10dBm configuration(5)		 +10dBm setting 2%
Error vector magnitude
Regular PA		 +5dBm setting 2%
(1) Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).
(2) To ensure margins for passing FCC band edge requirements at 2483.5MHz, a lower than maximum output-power setting or less than 100% duty cycle may be used when operating at 2480MHz.
(3) To ensure margins for passing FCC band edge requirements at 2483.5MHz, a lower than maximum output-power setting or less than 100% duty cycle may be used when operating at the upper 802.15.4 channel(s). 
(4) To ensure margins for passing FCC requirements for harmonic emission, duty cycling may be required. The CC1352P-2 LaunchPad reference design should also be reviewed as the filter provides higher attenuation of harmonics compared to the  CC1352PEM-XD7793-XD24-PA24 reference design.