SWRS206E March   2017  – May 2021 CC3220MOD , CC3220MODA

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Functional Block Diagrams
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 CC3220MODx and CC3220MODAx Pin Diagram
    2. 7.2 Pin Attributes
      1. 7.2.1 Module Pin Attributes
    3. 7.3 Connections for Unused Pins
    4. 7.4 Pin Attributes and Pin Multiplexing
    5. 7.5 Drive Strength and Reset States for Analog-Digital Multiplexed Pins
    6. 7.6 Pad State After Application of Power to Chip, but Before Reset Release
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Current Consumption (CC3220MODS and CC3220MODAS)
    5. 8.5  Current Consumption (CC3220MODSF and CC3220MODASF)
    6. 8.6  TX Power and IBAT Versus TX Power Level Settings
    7. 8.7  Brownout and Blackout Conditions
    8. 8.8  Electrical Characteristics
    9. 8.9  CC3220MODAx Antenna Characteristics
    10. 8.10 WLAN Receiver Characteristics
    11. 8.11 WLAN Transmitter Characteristics
    12. 8.12 Reset Requirement
    13. 8.13 Thermal Resistance Characteristics for MOB and MON Packages
    14. 8.14 Timing and Switching Characteristics
      1. 8.14.1 Power-Up Sequencing
      2. 8.14.2 Power-Down Sequencing
      3. 8.14.3 Device Reset
      4. 8.14.4 Wake Up From Hibernate Timing
      5. 8.14.5 Peripherals Timing
        1. 8.14.5.1  SPI
          1. 8.14.5.1.1 SPI Master
          2. 8.14.5.1.2 SPI Slave
        2. 8.14.5.2  I2S
          1. 8.14.5.2.1 I2S Transmit Mode
          2. 8.14.5.2.2 I2S Receive Mode
        3. 8.14.5.3  GPIOs
          1. 8.14.5.3.1 GPIO Input Transition Time Parameters
        4. 8.14.5.4  I2C
        5. 8.14.5.5  IEEE 1149.1 JTAG
        6. 8.14.5.6  ADC
        7. 8.14.5.7  Camera Parallel Port
        8. 8.14.5.8  UART
        9. 8.14.5.9  External Flash Interface
        10. 8.14.5.10 SD Host
        11. 8.14.5.11 Timers
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  Arm® Cortex®-M4 Processor Core Subsystem
    3. 9.3  Wi-Fi® Network Processor Subsystem
      1. 9.3.1 WLAN
      2. 9.3.2 Network Stack
    4. 9.4  Security
    5. 9.5  Power-Management Subsystem
      1. 9.5.1 VBAT Wide-Voltage Connection
    6. 9.6  Low-Power Operating Mode
    7. 9.7  Memory
      1. 9.7.1 Internal Memory
        1. 9.7.1.1 SRAM
        2. 9.7.1.2 ROM
        3. 9.7.1.3 Flash Memory
        4. 9.7.1.4 Memory Map
    8. 9.8  Restoring Factory Default Configuration
    9. 9.9  Boot Modes
      1. 9.9.1 Boot Mode List
    10. 9.10 Device Certification and Qualification
      1. 9.10.1 FCC Certification and Statement
      2. 9.10.2 Industry Canada (IC) Certification and Statement
      3. 9.10.3 ETSI/CE Certification
      4. 9.10.4 MIC Certification
      5. 9.10.5 SRRC Certification and Statement
    11. 9.11 Module Markings
    12. 9.12 End Product Labeling
    13. 9.13 Manual Information to the End User
  10. 10Applications, Implementation, and Layout
    1. 10.1 Typical Application
    2. 10.2 Device Connection and Layout Fundamentals
      1. 10.2.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.2.2 Reset
      3. 10.2.3 Unused Pins
    3. 10.3 PCB Layout Guidelines
      1. 10.3.1 General Layout Recommendations
      2. 10.3.2 CC3220MODx RF Layout Recommendations
        1. 10.3.2.1 Antenna Placement and Routing
        2. 10.3.2.2 Transmission Line Considerations
      3. 10.3.3 CC3220MODAx RF Layout Recommendations
  11. 11Environmental Requirements and Specifications
    1. 11.1 PCB Bending
    2. 11.2 Handling Environment
      1. 11.2.1 Terminals
      2. 11.2.2 Falling
    3. 11.3 Storage Condition
      1. 11.3.1 Moisture Barrier Bag Before Opened
      2. 11.3.2 Moisture Barrier Bag Open
    4. 11.4 Baking Conditions
    5. 11.5 Soldering and Reflow Condition
  12. 12Device and Documentation Support
    1. 12.1 Development Tools and Software
    2. 12.2 Firmware Updates
    3. 12.3 Device Nomenclature
    4. 12.4 Documentation Support
    5. 12.5 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical, Land, and Solder Paste Drawings
    2. 13.2 Package Option Addendum
      1. 13.2.1 Packaging Information
      2. 13.2.2 Tape and Reel Information
        1. 13.2.2.1 CC3220MODx Tape Specifications
        2. 13.2.2.2 CC3220MODAx Tape Specifications

7.2.1 Module Pin Attributes

MODULE PIN TYPE(1) CC3220 DEVICE PIN NO. MODULE PIN DESCRIPTION
NO. NAME
1 GND – – Ground
2 GND – – Ground
3 GPIO10 I/O 1 GPIO(2)
4 GPIO11 I/O 2 GPIO(2)
5 GPIO14 I/O 5 GPIO(2)
6 GPIO15 I/O 6 GPIO(2)
7 GPIO16 I/O 7 GPIO(2)
8 GPIO17 I/O 8 GPIO(2)
9 GPIO12 I/O 3 GPIO(2)
10 GPIO13 I/O 4 GPIO(2)
11 GPIO22 I/O 15 GPIO(2)
12 JTAG_TDI I/O 16 JTAG TDI input. Leave unconnected if not used on product(2)
13 FLASH_SPI_MISO I – External Serial Flash Programming: SPI data in
14 FLASH_SPI_nCS_IN I – External Serial Flash Programming: SPI chip select (active low)
15 FLASH_SPI_CLK I – External Serial Flash Programming: SPI clock
16 GND – – Ground
17 FLASH_SPI_MOSI O – External Serial Flash Programming: SPI data out
18 JTAG_TDO I/O 17 JTAG TDO output. Leave unconnected if not used on product(1)
19 GPIO28 I/O 18 GPIO(2)
21 JTAG_TCK I/O 19 JTAG TCK input. Leave unconnected if not used on product.(2)
22 JTAG_TMS I/O 20 JTAG TMS input. Leave unconnected if not used on product.(2)
23 SOP2 – 21 See Section 9.9.1 for SOP[2:0] configuration modes.
24 SOP1 – 34 See Section 9.9.1 for SOP[2:0] configuration modes.
25 ANT_SEL1 I/O 29 Antenna selection control(2)
26 ANT_SEL2 I/O 30 Antenna selection control(2)
27 GND – – Ground
28 GND – – Ground
30 GND – – Ground
31 RF_BG I/O 31 2.4-GHz RF input/output
32 GND – – Ground
34 SOP0 – 35 See Section 9.9.1 for SOP[2:0] configuration modes.
35 nRESET I 32 There is an internal, 100 kΩ, pull-up resistor option from the nRESET pin to VBAT_RESET. Note: VBAT_RESET is not connected to VBAT1 or VBAT2 within the module. The following connection schemes are recommended:
  • Connect nRESET to a switch, external controller, or host, only if nRESET will be in a defined state under all operating conditions. Leave VBAT_RESET unconnected to save power.
  • If nRESET cannot be in a defined state under all operating conditions, connect VBAT_RESET to the main module power supply (VBAT1 and VBAT2). Due to the internal pull-up resistor a leakage current of 3.3 V / 100 kΩ is expected.
36 VBAT_RESET – 37
37 VBAT1 Power 39 Power supply for the module, must be connected to battery (2.3 V to 3.6 V)
38 GND – – Ground
40 VBAT2 Power 10, 44, 54 Power supply for the module, must be connected to battery (2.3 V to 3.6 V)
42 GPIO30 I/O 53 GPIO(2)
43 GND – – Ground
44 GPIO0 I/O 50 GPIO(2)
46 GPIO1 I/O 55 GPIO(2)
47 GPIO2 I/O 57 GPIO(2)
48 GPIO3 I/O 58 GPIO(2)
49 GPIO4 I/O 59 GPIO(2)
50 GPIO5 I/O 60 GPIO(2)
51 GPIO6 I/O 61 GPIO(2)
52 GPIO7 I/O 62 GPIO(2)
53 GPIO8 I/O 63 GPIO(2)
54 GPIO9 I/O 64 GPIO(2)
55 GND – – Thermal ground
56 GND – – Thermal ground
57 GND – – Thermal ground
58 GND – – Thermal ground
59 GND – – Thermal ground
60 GND – – Thermal ground
61 GND – – Thermal ground
62 GND – – Thermal ground
63 GND – – Thermal ground
(1) I = input; O = output; I/O = bidirectional
(2) For pin multiplexing details, see Table 7-3.