SWRS211C May   2017  – October 2018 IWR1443

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
    3. 4.3 Pin Multiplexing
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Power Supply Specifications
    6. 5.6 Power Consumption Summary
    7. 5.7 RF Specification
    8. 5.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 5.9 Timing and Switching Characteristics
      1. 5.9.1  Power Supply Sequencing and Reset Timing
      2. 5.9.2  Synchronized Frame Triggering
      3. 5.9.3  Input Clocks and Oscillators
        1. 5.9.3.1 Clock Specifications
      4. 5.9.4  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 5.9.4.1 Peripheral Description
        2. 5.9.4.2 MibSPI Transmit and Receive RAM Organization
          1. Table 5-8  SPI Timing Conditions
          2. Table 5-9  SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. Table 5-10 SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 5.9.4.3 SPI Slave Mode I/O Timings
          1. Table 5-11 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        4. 5.9.4.4 Typical Interface Protocol Diagram (Slave Mode)
      5. 5.9.5  LVDS Interface Configuration
        1. 5.9.5.1 LVDS Interface Timings
      6. 5.9.6  General-Purpose Input/Output
        1. Table 5-13 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 5.9.7  Controller Area Network Interface (DCAN)
        1. Table 5-14 Dynamic Characteristics for the DCANx TX and RX Pins
      8. 5.9.8  Serial Communication Interface (SCI)
        1. Table 5-15 SCI Timing Requirements
      9. 5.9.9  Inter-Integrated Circuit Interface (I2C)
        1. Table 5-16 I2C Timing Requirements
      10. 5.9.10 Quad Serial Peripheral Interface (QSPI)
        1. Table 5-17 QSPI Timing Conditions
        2. Table 5-18 Timing Requirements for QSPI Input (Read) Timings
        3. Table 5-19 QSPI Switching Characteristics
      11. 5.9.11 JTAG Interface
        1. Table 5-20 JTAG Timing Conditions
        2. Table 5-21 Timing Requirements for IEEE 1149.1 JTAG
        3. Table 5-22 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
      12. 5.9.12 Camera Serial Interface (CSI)
        1. Table 5-23 CSI Switching Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 External Interfaces
    4. 6.4 Subsystems
      1. 6.4.1 RF and Analog Subsystem
        1. 6.4.1.1 Clock Subsystem
        2. 6.4.1.2 Transmit Subsystem
        3. 6.4.1.3 Receive Subsystem
        4. 6.4.1.4 Radio Processor Subsystem
      2. 6.4.2 Master (Control) System
      3. 6.4.3 Host Interface
    5. 6.5 Accelerators and Coprocessors
    6. 6.6 Other Subsystems
      1. 6.6.1 A2D Data Format Over CSI2 Interface
      2. 6.6.2 ADC Channels (Service) for User Application
        1. Table 6-2 GP-ADC Parameter
    7. 6.7 Identification
    8. 6.8 Boot Modes
      1. 6.8.1 Flashing Mode
      2. 6.8.2 Functional Mode
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Reference Schematic
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
      3. 7.3.3 Stackup Details
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Community Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Export Control Notice
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information

4.3 Pin Multiplexing

Table 4-2 Pin Multiplexing

REGISTER ADDRESS(1) PIN NAME PIN DIGITAL PIN MUX CONFIG VALUE [Bits3:0] FUNCTION PAD STATE
nReset = 0 [ASSERTED]
SIGNAL NAME SIGNAL DESCRIPTION SIGNAL TYPE STATE INTERNAL WEAK PULL STATE
EA00h GPIO_12 P6 0 GPIO_12 General Purpose IO IO Hi-Z Weak Pull Down
1 SPI_HOST1_INTR General Purpose IO [IWR14xx] O
EA04h GPIO_0 N4 0 GPIO_13 General Purpose IO IO Hi-Z Weak Pull Down
1 GPIO_0 General Purpose IO IO
2 PMIC_CLKOUT Dithered Clock Output for PMIC O
EA08h GPIO_1 N7 0 GPIO_16 General Purpose IO IO Hi-Z Weak Pull Down
1 GPIO_1 General Purpose IO IO
2 SYNC_OUT Low Frequency Synchronization Signal output O
EA0Ch MOSI_1 R8 0 GPIO_19 General Purpose IO IO Hi-Z Weak Pull Up
1 MOSI_1 SPI Channel#1 Data Input IO
2 CAN_RX CAN Interface I
EA10h MISO_1 P5 0 GPIO_20 General Purpose IO IO Hi-Z Weak Pull Up
1 MISO_1 SPI Channel#1 Data Output IO
2 CAN_TX CAN Interface O
EA14h SPI_CLK_1 R9 0 GPIO_3 General Purpose IO IO Hi-Z Weak Pull Up
1 SPI_CLK_1 SPI Channel#1 Clock IO
RCOSC_CLK O
EA18h SPI_CS_1 R7 0 GPIO_30 General Purpose IO IO Hi-Z Weak Pull Up
1 SPI_CS_1 SPI Channel#1 Chip Select IO
RCOSC_CLK O
EA1Ch MOSI_2 R3 0 GPIO_21 General Purpose IO IO Hi-Z
1 MOSI_2 SPI Channel#2 Data Input IO
2 I2C_SDA I2C Data IO
EA20h MISO_2 P4 0 GPIO_22 General Purpose IO IO Hi-Z
1 MISO_2 SPI Channel#2 Data Output IO
2 I2C_SCL I2C Clock IO
EA24h SPI_CLK_2 R5 0 GPIO_5 General Purpose IO IO Hi-Z
1 SPI_CLK_2 SPI Channel#2 Clock IO
MSS_UARTA_RX IO
6 MSS_UARTB_TX Debug: Firmware Trace O
7 BSS_UART_TX Debug: Firmware Trace O
EA28h SPI_CS_2 R4 0 GPIO_4 General Purpose IO IO Hi-Z
1 SPI_CS_2 SPI Channel#2 Chip Select IO
MSS_UARTA_TX IO
6 MSS_UARTB_TX Debug: Firmware Trace O
7 BSS_UART_TX Debug: Firmware Trace O
EA2Ch QSPI[0] R11 0 GPIO_8 General Purpose IO IO Hi-Z Weak Pull Down
1 QSPI[0] QSPI Data IN/OUT IO
2 MISO_2 SPI Channel#1 Data Output IO
EA30h QSPI[1] P9 0 GPIO_9 General Purpose IO IO Hi-Z Weak Pull Down
1 QSPI[1] QSPI Data IN/OUT IO
2 MOSI_2 SPI Channel#2 Data Input IO
EA34h QSPI[2] R12 0 GPIO_10 General Purpose IO IO Hi-Z Weak Pull Down
1 QSPI[2] QSPI Data IN/OUT IO
EA38h QSPI[3] P10 0 GPIO_11 General Purpose IO IO Hi-Z Weak Pull Down
1 QSPI[3] QSPI Data IN/OUT I
EA3Ch QSPI_CLK R10 0 GPIO_7 General Purpose IO IO Hi-Z Weak Pull Down
1 QSPI_CLK QSPI Clock output from the device.
Device operates as a master with the serial flash being a slave		 O
2 SPI_CLK_2 SPI Channel#2 Clock IO
EA40h QSPI_CS P8 0 GPIO_6 General Purpose IO IO Hi-Z Weak Pull Up
1 QSPI_CS QSPI Chip Select output from the device.
Device operates as a master with the serial flash being a slave		 O
2 SPI_CS_2 SPI Channel#2 Chip Select IO
NERROR_IN P7 NERROR_IN Failsafe input to the device. Nerror output from any other device can be concentrated in the error signaling monitor module inside the device and appropriate action can be taken by Firmware I Hi-Z
WARM_RESET N12 WARM_RESET Open drain fail safe warm reset signal. Can be driven from PMIC for diagnostic or can be used as status signal that the device is going through reset. IO Hi-Z Input Open Drain
NERROR_OUT N8 NERROR_OUT Open drain fail safe output signal. Connected to PMIC/Processor/MCU to indicate that some severe criticality fault has happened. Recovery would be through reset. O Hi-Z Open Drain
EA50h TCK M13 0 GPIO_17 General Purpose IO IO Hi-Z Weak Pull Down
1 TCK JTAG Clock I
2 MSS_UARTB_TX Debug: Firmware Trace O
6 BSS_UART_RX Debug: Firmware Trace I
EA54h TMS L13 0 GPIO_18 General Purpose IO IO Hi-Z Weak Pull Up
1 TMS JTAG Test Mode Select IO
2 BSS_UART_TX Debug: Firmware Trace O
EA58h TDI H13 0 GPIO_23 General Purpose IO IO Hi-Z Weak Pull Up
1 TDI JTAG Test Data In I
MSS_UARTA_RX IO
EA5Ch TDO J13 0 GPIO_24 General Purpose IO IO Hi-Z
1 TDO JTAG Test Data Out O
MSS_UARTA_TX IO
6 MSS_UARTB_TX Debug: Firmware Trace O
7 BSS_UART_TX Debug: Firmware Trace O
SOP0 Sense On Power [Reset] Line
Impacts boot mode		 I
EA60h MCU_CLKOUT N9 0 GPIO_25 General Purpose IO IO Hi-Z Weak Pull Down
1 MCU_CLKOUT Programmable clock given out to external MCU or the processor O
10 BSS_UART_RX Debug: Firmware Trace I
EA64h GPIO_2 N13 0 GPIO_26 General Purpose IO IO Hi-Z Weak Pull Down
1 GPIO_2 General Purpose IO IO
7 MSS_UARTB_TX Debug: Firmware Trace O
8 BSS_UART_TX Debug: Firmware Trace O
9 SYNC_OUT Low frequency Synchronization signal output O
10 PMIC_CLKOUT Dithered clock input to PMIC O
EA68h PMIC_CLKOUT P13 0 GPIO_27 General Purpose IO IO Hi-Z Weak Pull Down
1 PMIC_CLKOUT Dithered Clock Output for PMIC O
SOP2 Sense On Power [Reset] Line
Impacts boot mode		 I
EA6Ch SYNC_IN N10 0 GPIO_28 General Purpose IO IO Hi-Z Weak Pull Down
1 SYNC_IN Low frequency Synchronization signal input I
6 MSS_UARTB_RX Debug: Firmware Trace I
EA70h SYNC_OUT P11 0 GPIO_29 General Purpose IO IO Hi-Z Weak Pull Down
1 SYNC_OUT Low frequency Synchronization signal output O
RCOSC_CLK O
SOP1 Sense On Power [Reset] Line
Impacts boot mode		 I
EA74h RS232_RX N5 0 GPIO_15 General Purpose IO IO Hi-Z Weak Pull Up
1 RS232_RX Debug: Firmware load to RAM IO
2 MSS_UARTA_RX FLASH Programming
Bootloader Controlled		 I
6 BSS_UART_TX Debug: Firmware Trace O
7 MSS_UARTB_RX Debug: Firmware Trace I
EA78h RS232_TX N6 0 GPIO_14 General Purpose IO IO
1 RS232_TX Debug: Firmware load to RAM IO
5 MSS_UARTA_TX FLASH Programming
Bootloader Controlled		 O
6 MSS_UARTB_TX Debug: Firmware Trace O
7 BSS_UART_TX Debug: Firmware Trace O
(1) Register addresses are of the form FFFF XXXXh, where XXXX is listed here.