SWRS212B
May 2017 – April 2018
IWR1642
PRODUCTION DATA.
1
Device Overview
1.1
Features
1.2
Applications
1.3
Description
1.4
Functional Block Diagram
2
Revision History
3
Device Comparison
3.1
Related Products
4
Terminal Configuration and Functions
4.1
Pin Diagram
4.2
Pin Attributes
Table 4-3
PAD IO Register Bit Descriptions
4.3
Signal Descriptions
Table 4-4
Signal Descriptions - Digital
Table 4-5
Signal Descriptions - Analog
4.4
Pin Multiplexing
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Power-On Hours (POH)
5.4
Recommended Operating Conditions
5.5
Power Supply Specifications
5.6
Power Consumption Summary
5.7
RF Specification
5.8
CPU Specifications
5.9
Thermal Resistance Characteristics for FCBGA Package [ABL0161]
5.10
Timing and Switching Characteristics
5.10.1
Power Supply Sequencing and Reset Timing
5.10.2
Input Clocks and Oscillators
5.10.2.1
Clock Specifications
5.10.3
Multibuffered / Standard Serial Peripheral Interface (MibSPI)
5.10.3.1
Peripheral Description
5.10.3.2
MibSPI Transmit and Receive RAM Organization
Table 5-7
SPI Timing Conditions
Table 5-8
SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
Table 5-9
SPI Master Mode Input Timing Requirements (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
Table 5-10
SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
Table 5-11
SPI Master Mode Input Requirements (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
5.10.3.3
SPI Slave Mode I/O Timings
Table 5-12
SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
Table 5-13
SPI Slave Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
5.10.3.4
Typical Interface Protocol Diagram (Slave Mode)
5.10.4
LVDS Interface Configuration
5.10.4.1
LVDS Interface Timings
5.10.5
General-Purpose Input/Output
Table 5-15
Switching Characteristics for Output Timing versus Load Capacitance (CL)
5.10.6
Controller Area Network Interface (DCAN)
Table 5-16
Dynamic Characteristics for the DCANx TX and RX Pins
5.10.7
Serial Communication Interface (SCI)
Table 5-17
SCI Timing Requirements
5.10.8
Inter-Integrated Circuit Interface (I2C)
Table 5-18
I2C Timing Requirements
5.10.9
Quad Serial Peripheral Interface (QSPI)
Table 5-19
QSPI Timing Conditions
Table 5-20
Timing Requirements for QSPI Input (Read) Timings
Table 5-21
QSPI Switching Characteristics
5.10.10
ETM Trace Interface
Table 5-22
ETMTRACE Timing Conditions
Table 5-23
ETM TRACE Switching Characteristics
5.10.11
Data Modification Module (DMM)
Table 5-24
DMM Timing Requirements
5.10.12
JTAG Interface
Table 5-25
JTAG Timing Conditions
Table 5-26
Timing Requirements for IEEE 1149.1 JTAG
Table 5-27
Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Subsystems
6.3.1
RF and Analog Subsystem
6.3.1.1
Clock Subsystem
6.3.1.2
Transmit Subsystem
6.3.1.3
Receive Subsystem
6.3.2
Processor Subsystem
6.3.3
Host Interface
6.3.4
Master Subsystem Cortex-R4F Memory Map
6.3.5
DSP Subsystem Memory Map
6.4
Other Subsystems
6.4.1
ADC Channels (Service) for User Application
Table 6-3
GP-ADC Parameter
7
Monitoring and Diagnostics
7.1
Monitoring and Diagnostic Mechanisms
7.1.1
Error Signaling Module
8
Applications, Implementation, and Layout
8.1
Application Information
8.2
Reference Schematic
8.3
Layout
8.3.1
Layout Guidelines
8.3.2
Layout Example
8.3.3
Stackup Details
9
Device and Documentation Support
9.1
Device Nomenclature
9.2
Tools and Software
9.3
Documentation Support
9.4
Community Resources
9.5
Trademarks
9.6
Electrostatic Discharge Caution
9.7
Export Control Notice
9.8
Glossary
10
Mechanical, Packaging, and Orderable Information
10.1
Packaging Information
10.1
Packaging Information
5.10.3
Multibuffered / Standard Serial Peripheral Interface (MibSPI)