SWRS219E October 2018 – June 2021 IWR6443 , IWR6843
PRODUCTION DATA
BALL NUMBER [1] | BALL NAME [2] | SIGNAL NAME [3] | PINCNTL ADDRESS[4] | MODE [5][9] | TYPE [6] | BALL RESET STATE [7] | PULL UP/DOWN TYPE [8] |
---|---|---|---|---|---|---|---|
H13 | GPIO_0 | GPIO_13 | 0xFFFFEA04 | 0 | IO | Output Disabled | Pull Down |
GPIO_0 | 1 | IO | |||||
PMIC_CLKOUT | 2 | O | |||||
EPWM1B | 10 | O | |||||
ePWM2A | 11 | O | |||||
J13 | GPIO_1 | GPIO_16 | 0xFFFFEA08 | 0 | IO | Output Disabled | Pull Down |
GPIO_1 | 1 | IO | |||||
SYNC_OUT | 2 | O | |||||
DMM_MUX_IN | 12 | I | |||||
SPIB_CS_N_1 | 13 | IO | |||||
SPIB_CS_N_2 | 14 | IO | |||||
EPWM1SYNCI | 15 | I | |||||
K13 | GPIO_2 | GPIO_26 | 0xFFFFEA64 | 0 | IO | Output Disabled | Pull Down |
GPIO_2 | 1 | IO | |||||
OSC_CLKOUT | 2 | O | |||||
MSS_UARTB_TX | 7 | O | |||||
BSS_UART_TX | 8 | O | |||||
SYNC_OUT | 9 | O | |||||
PMIC_CLKOUT | 10 | O | |||||
CHIRP_START | 11 | O | |||||
CHIRP_END | 12 | O | |||||
FRAME_START | 13 | O | |||||
R4 | GPIO_31 | TRACE_DATA_0 | 0xFFFFEA7C | 0 | O | Output Disabled | Pull Down |
GPIO_31 | 1 | IO | |||||
DMM0 | 2 | I | |||||
MSS_UARTA_TX | 4 | IO | |||||
P5 | GPIO_32 | TRACE_DATA_1 | 0xFFFFEA80 | 0 | O | Output Disabled | Pull Down |
GPIO_32 | 1 | IO | |||||
DMM1 | 2 | I | |||||
R5 | GPIO_33 | TRACE_DATA_2 | 0xFFFFEA84 | 0 | O | Output Disabled | Pull Down |
GPIO_33 | 1 | IO | |||||
DMM2 | 2 | I | |||||
P6 | GPIO_34 | TRACE_DATA_3 | 0xFFFFEA88 | 0 | O | Output Disabled | Pull Down |
GPIO_34 | 1 | IO | |||||
DMM3 | 2 | I | |||||
EPWM3SYNCO | 4 | O | |||||
R7 | GPIO_35 | TRACE_DATA_4 | 0xFFFFEA8C | 0 | O | Output Disabled | Pull Down |
GPIO_35 | 1 | IO | |||||
DMM4 | 2 | I | |||||
EPWM2SYNCO | 4 | O | |||||
P7 | GPIO_36 | TRACE_DATA_5 | 0xFFFFEA90 | 0 | O | Output Disabled | Pull Down |
GPIO_36 | 1 | IO | |||||
DMM5 | 2 | I | |||||
MSS_UARTB_TX | 5 | O | |||||
R8 | GPIO_37 | TRACE_DATA_6 | 0xFFFFEA94 | 0 | O | Output Disabled | Pull Down |
GPIO_37 | 1 | IO | |||||
DMM6 | 2 | I | |||||
BSS_UART_TX | 5 | O | |||||
P8 | GPIO_38 | TRACE_DATA_7 | 0xFFFFEA98 | 0 | O | Output Disabled | Pull Down |
GPIO_38 | 1 | IO | |||||
DMM7 | 2 | I | |||||
DSS_UART_TX | 5 | O | |||||
N15 | GPIO_47 | TRACE_CLK | 0xFFFFEABC | 0 | O | Output Disabled | Pull Down |
GPIO_47 | 1 | IO | |||||
DMM_CLK | 2 | I | |||||
N14 | DMM_SYNC | TRACE_CTL | 0xFFFFEAC0 | 0 | O | Output Disabled | Pull Down |
DMM_SYNC | 2 | I | |||||
N8 | MCU_CLKOUT | GPIO_25 | 0xFFFFEA60 | 0 | IO | Output Disabled | Pull Down |
MCU_CLKOUT | 1 | O | |||||
CHIRP_START | 2 | O | |||||
CHIRP_END | 6 | O | |||||
FRAME_START | 7 | O | |||||
EPWM1A | 12 | O | |||||
N7 | NERROR_IN | NERROR_IN | 0xFFFFEA44 | 0 | I | Input | |
N6 | NERROR_OUT | NERROR_OUT | 0xFFFFEA4C | 0 | O | Hi-Z (Open Drain) | |
P9 | PMIC_CLKOUT | SOP[2] | 0xFFFFEA68 | During Power Up | I | Output Disabled | Pull Down |
GPIO_27 | 0 | IO | |||||
PMIC_CLKOUT | 1 | O | |||||
CHIRP_START | 6 | O | |||||
CHIRP_END | 7 | O | |||||
FRAME_START | 8 | O | |||||
EPWM1B | 11 | O | |||||
EPWM2A | 12 | O | |||||
R13 | QSPI[0] | GPIO_8 | 0xFFFFEA2C | 0 | IO | Output Disabled | Pull Down |
QSPI[0] | 1 | IO | |||||
SPIB_MISO | 2 | IO | |||||
N12 | QSPI[1] | GPIO_9 | 0xFFFFEA30 | 0 | IO | Output Disabled | Pull Down |
QSPI[1] | 1 | I | |||||
SPIB_MOSI | 2 | IO | |||||
SPIB_CS_N_2 | 8 | IO | |||||
R14 | QSPI[2] | GPIO_10 | 0xFFFFEA34 | 0 | IO | Output Disabled | Pull Down |
QSPI[2] | 1 | I | |||||
CAN_FD_TX | 8 | O | |||||
P12 | QSPI[3] | GPIO_11 | 0xFFFFEA38 | 0 | IO | Output Disabled | Pull Down |
QSPI[3] | 1 | I | |||||
CAN_FD_RX | 8 | I | |||||
R12 | QSPI_CLK | GPIO_7 | 0xFFFFEA3C | 0 | IO | Output Disabled | Pull Down |
QSPI_CLK | 1 | O | |||||
SPIB_CLK | 2 | IO | |||||
DSS_UART_TX | 6 | O | |||||
P11 | QSPI_CS_N | GPIO_6 | 0xFFFFEA40 | 0 | IO | Output Disabled | Pull Up |
QSPI_CS_N | 1 | O | |||||
SPIB_CS_N | 2 | IO | |||||
N4 | RS232_RX | GPIO_15 | 0xFFFFEA74 | 0 | IO | Input Enabled | Pull Up |
RS232_RX | 1 | I | |||||
MSS_UARTA_RX | 2 | I | |||||
BSS_UART_TX | 6 | IO | |||||
MSS_UARTB_RX | 7 | IO | |||||
CAN_FD_RX | 8 | I | |||||
I2C_SCL | 9 | IO | |||||
EPWM2A | 10 | O | |||||
EPWM2B | 11 | O | |||||
EPWM3A | 12 | O | |||||
N5 | RS232_TX | GPIO_14 | 0xFFFFEA78 | 0 | IO | Output Enabled | |
RS232_TX | 1 | O | |||||
MSS_UARTA_TX | 5 | IO | |||||
MSS_UARTB_TX | 6 | IO | |||||
BSS_UART_TX | 7 | IO | |||||
CAN_FD_TX | 10 | O | |||||
I2C_SDA | 11 | IO | |||||
EPWM1A | 12 | O | |||||
EPWM1B | 13 | O | |||||
NDMM_EN | 14 | I | |||||
EPWM2A | 15 | O | |||||
E13 | SPIA_CLK | GPIO_3 | 0xFFFFEA14 | 0 | IO | Output Disabled | Pull Up |
SPIA_CLK | 1 | IO | |||||
DSS_UART_TX | 7 | O | |||||
E15 | SPIA_CS_N | GPIO_30 | 0xFFFFEA18 | 0 | IO | Output Disabled | Pull Up |
SPIA_CS_N | 1 | IO | |||||
E14 | SPIA_MISO | GPIO_20 | 0xFFFFEA10 | 0 | IO | Output Disabled | Pull Up |
SPIA_MISO | 1 | IO | |||||
CAN_FD_TX | 2 | O | |||||
D13 | SPIA_MOSI | GPIO_19 | 0xFFFFEA0C | 0 | IO | Output Disabled | Pull Up |
SPIA_MOSI | 1 | IO | |||||
CAN_FD_RX | 2 | I | |||||
DSS_UART_TX | 8 | O | |||||
F14 | SPIB_CLK | GPIO_5 | 0xFFFFEA24 | 0 | IO | Output Disabled | Pull Up |
SPIB_CLK | 1 | IO | |||||
MSS_UARTA_RX | 2 | I | |||||
MSS_UARTB_TX | 6 | O | |||||
BSS_UART_TX | 7 | O | |||||
CAN_FD_RX | 8 | I | |||||
H14 | SPIB_CS_N | GPIO_4 | 0xFFFFEA28 | 0 | IO | Output Disabled | Pull Up |
SPIB_CS_N | 1 | IO | |||||
MSS_UARTA_TX | 2 | O | |||||
MSS_UARTB_TX | 6 | O | |||||
BSS_UART_TX | 7 | IO | |||||
QSPI_CLK_EXT | 8 | I | |||||
CAN_FD_TX | 9 | O | |||||
G14 | SPIB_MISO | GPIO_22 | 0xFFFFEA20 | 0 | IO | Output Disabled | Pull Up |
SPIB_MISO | 1 | IO | |||||
I2C_SCL | 2 | IO | |||||
DSS_UART_TX | 6 | O | |||||
F13 | SPIB_MOSI | GPIO_21 | 0xFFFFEA1C | 0 | IO | Output Disabled | Pull Up |
SPIB_MOSI | 1 | IO | |||||
I2C_SDA | 2 | IO | |||||
P13 | SPI_HOST_INTR | GPIO_12 | 0xFFFFEA00 | 0 | IO | Output Disabled | Pull Down |
SPI_HOST_INTR | 1 | O | |||||
SPIB_CS_N_1 | 6 | IO | |||||
P4 | SYNC_IN | GPIO_28 | 0xFFFFEA6C | 0 | IO | Output Disabled | Pull Down |
SYNC_IN | 1 | I | |||||
MSS_UARTB_RX | 6 | IO | |||||
DMM_MUX_IN | 7 | I | |||||
SYNC_OUT | 9 | O | |||||
G13 | SYNC_OUT | SOP[1] | 0xFFFFEA70 | During Power Up | I | Output Disabled | Pull Down |
GPIO_29 | 0 | IO | |||||
SYNC_OUT | 1 | O | |||||
DMM_MUX_IN | 9 | I | |||||
SPIB_CS_N_1 | 10 | IO | |||||
SPIB_CS_N_2 | 11 | IO | |||||
P10 | TCK | GPIO_17 | 0xFFFFEA50 | 0 | IO | Input Enabled | Pull Down |
TCK | 1 | I | |||||
MSS_UARTB_TX | 2 | O | |||||
CAN_FD_TX | 8 | O | |||||
R11 | TDI | GPIO_23 | 0xFFFFEA58 | 0 | IO | Input Enabled | Pull Up |
TDI | 1 | I | |||||
MSS_UARTA_RX | 2 | I | |||||
N13 | TDO | SOP[0] | 0xFFFFEA5C | During Power Up | I | Output Enabled | |
GPIO_24 | 0 | IO | |||||
TDO | 1 | O | |||||
MSS_UARTA_TX | 2 | O | |||||
MSS_UARTB_TX | 6 | O | |||||
BSS_UART_TX | 7 | O | |||||
NDMM_EN | 9 | I | |||||
N10 | TMS | GPIO_18 | 0xFFFFEA54 | 0 | IO | Input Enabled | Pull Down |
TMS | 1 | I | |||||
BSS_UART_TX | 2 | O | |||||
CAN_FD_RX | 6 | I | |||||
N9 | WARM_RESET | WARM_RESET | 0xFFFFEA48 | 0 | IO | Hi-Z Input (Open Drain) |
The following list describes the table column headers:
IO MUX registers are available in the MSS memory map and the respective mapping to device pins is as follows:
Default Pin/Ball Name | Package Ball /Pin (Address) | Pin Mux Config Register |
---|---|---|
SPI_HOST_INTR | P13 | 0xFFFFEA00 |
GPIO_0 | H13 | 0xFFFFEA04 |
GPIO_1 | J13 | 0xFFFFEA08 |
SPIA_MOSI | D13 | 0xFFFFEA0C |
SPIA_MISO | E14 | 0xFFFFEA10 |
SPIA_CLK | E13 | 0xFFFFEA14 |
SPIA_CS_N | E15 | 0xFFFFEA18 |
SPIB_MOSI | F13 | 0xFFFFEA1C |
SPIB_MISO | G14 | 0xFFFFEA20 |
SPIB_CLK | F14 | 0xFFFFEA24 |
SPIB_CS_N | H14 | 0xFFFFEA28 |
QSPI[0] | R13 | 0xFFFFEA2C |
QSPI[1] | N12 | 0xFFFFEA30 |
QSPI[2] | R14 | 0xFFFFEA34 |
QSPI[3] | P12 | 0xFFFFEA38 |
QSPI_CLK | R12 | 0xFFFFEA3C |
QSPI_CS_N | P11 | 0xFFFFEA40 |
NERROR_IN | N7 | 0xFFFFEA44 |
WARM_RESET | N9 | 0xFFFFEA48 |
NERROR_OUT | N6 | 0xFFFFEA4C |
TCK | P10 | 0xFFFFEA50 |
TMS | N10 | 0xFFFFEA54 |
TDI | R11 | 0xFFFFEA58 |
TDO | N13 | 0xFFFFEA5C |
MCU_CLKOUT | N8 | 0xFFFFEA60 |
GPIO_2 | K13 | 0xFFFFEA64 |
PMIC_CLKOUT | P9 | 0xFFFFEA68 |
SYNC_IN | P4 | 0xFFFFEA6C |
SYNC_OUT | G13 | 0xFFFFEA70 |
RS232_RX | N4 | 0xFFFFEA74 |
RS232_TX | N5 | 0xFFFFEA78 |
GPIO_31 | R4 | 0xFFFFEA7C |
GPIO_32 | P5 | 0xFFFFEA80 |
GPIO_33 | R5 | 0xFFFFEA84 |
GPIO_34 | P6 | 0xFFFFEA88 |
GPIO_35 | R7 | 0xFFFFEA8C |
GPIO_36 | P7 | 0xFFFFEA90 |
GPIO_37 | R8 | 0xFFFFEA94 |
GPIO_38 | P8 | 0xFFFFEA98 |
GPIO_47 | N15 | 0xFFFFEABC |
DMM_SYNC | N14 | 0xFFFFEAC0 |
The register layout is as follows:
BIT | FIELD | TYPE | RESET (POWER ON DEFAULT) | DESCRIPTION |
---|---|---|---|---|
31-11 | NU | RW | 0 | Reserved |
10 | SC | RW | 0 | IO slew rate
control: 0 = Higher slew rate 1 = Lower slew rate |
9 | PUPDSEL | RW | 0 | Pullup/PullDown
Selection 0 = Pull Down 1 = Pull Up (This field is valid only if Pull Inhibit is set as '0') |
8 | PI | RW | 0 | Pull Inhibit/Pull
Disable 0 = Enable 1 = Disable |
7 | OE_OVERRIDE | RW | 1 | Output Override |
6 | OE_OVERRIDE_CTRL | RW | 1 | Output Override
Control: (A '1' here overrides any o/p manipulation of this IO by any of the peripheral block hardware it is associated with for example a SPI Chip select) |
5 | IE_OVERRIDE | RW | 0 | Input Override |
4 | IE_OVERRIDE_CTRL | RW | 0 | Input Override
Control: (A '1' here overrides any i/p value on this IO with a desired value) |
3-0 | FUNC_SEL | RW | 1 | Function select for Pin Multiplexing (Refer to the Pin Mux Sheet) |