SWRS223D February   2020  – February 2024 AWR2243

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Signal Descriptions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Power-On Hours (POH)
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Power Supply Specifications
    6. 7.6 Power Consumption Summary
    7. 7.7 RF Specification
    8. 7.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 7.9 Timing and Switching Characteristics
      1. 7.9.1 Power Supply Sequencing and Reset Timing
      2. 7.9.2 Synchronized Frame Triggering
      3. 7.9.3 Input Clocks and Oscillators
        1. 7.9.3.1 Clock Specifications
      4. 7.9.4 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.9.4.1 Peripheral Description
          1. 7.9.4.1.1 SPI Timing Conditions
          2. 7.9.4.1.2 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
          3. 7.9.4.1.3 SPI Peripheral Mode Timing Requirements (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        2. 7.9.4.2 Typical Interface Protocol Diagram (Peripheral Mode)
      5. 7.9.5 Inter-Integrated Circuit Interface (I2C)
        1. 7.9.5.1 I2C Timing Requirements
      6. 7.9.6 LVDS Interface Configuration
        1. 7.9.6.1 LVDS Interface Timings
      7. 7.9.7 General-Purpose Input/Output
        1. 7.9.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      8. 7.9.8 Camera Serial Interface (CSI)
        1. 7.9.8.1 CSI Switching Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
      2. 8.3.2 Host Interface
    4. 8.4 Other Subsystems
      1. 8.4.1 ADC Data Format Over CSI2 Interface
      2. 8.4.2 ADC Channels (Service) for User Application
        1. 8.4.2.1 GPADC Parameters
  10. 9 Monitoring and Diagnostic Mechanisms
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Short-, Medium-, and Long-Range Radar
    3. 10.3 Imaging Radar using Cascade Configuration
    4. 10.4 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Export Control Notice
    8. 11.8 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information

1 Features

  • FMCW transceiver
    • Integrated PLL, transmitter, receiver, baseband, and ADC
    • 76GHz to 81GHz coverage with 5GHz available bandwidth
    • Four receive channels
    • Three transmit channels
    • Ultra-accurate chirp engine based on Fractional-N PLL
    • TX power: 13dBm
    • RX noise figure: 13dB
    • Phase noise at 1MHz:
      • –96dBc/Hz (76GHz to 77GHz)
      • –94dBc/Hz (77GHz to 81GHz)
  • Built-in calibration and self-test
    • Built-in firmware (ROM)
    • Self-calibrating system across process and temperature
  • Host interface
    • Control interface with external processor over SPI or I2C interface
    • Data interface with external processor over MIPI D-PHY and CSI2 v1.1
    • Interrupts for Fault Reporting
  • Functional Safety-Compliant
    • Developed for functional safety applications
    • Documentation available to aid ISO 26262 functional safety system design up to ASIL-D
    • Hardware integrity up to ASIL-B
    • Safety-related certification
      • ISO 26262 certified up to ASIL B by TUV SUD
  • AEC-Q100 qualified
  • AWR2243 advanced features
    • Embedded self-monitoring with limited Host processor involvement
    • Complex baseband architecture
    • Option of cascading multiple devices to increase channel count
    • Embedded interference detection capability
  • Power management
    • Built-in LDO Network for enhanced PSRR
    • I/Os support dual voltage 3.3V/1.8V
  • Clock source
    • Supports externally driven clock (square/sine) at 40MHz
    • Supports 40MHz crystal connection with load capacitors
  • Easy hardware design
    • 0.65mm pitch, 161-pin 10.4mm × 10.4mm flip chip BGA package for easy assembly and low-cost PCB design
    • Small solution size
  • Operating Conditions
    • Junction temp range: –40°C to 140°C