SWRS228B September   2019  – September 2024 IWR1843

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Signal Descriptions
      1. 6.2.1 Signal Descriptions - Digital
      2. 6.2.2 Signal Descriptions - Analog
    3. 6.3 Pin Attributes
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Supply Specifications
    6. 7.6  Power Consumption Summary
    7. 7.7  RF Specification
    8. 7.8  CPU Specifications
    9. 7.9  Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1  Power Supply Sequencing and Reset Timing
      2. 7.10.2  Input Clocks and Oscillators
        1. 7.10.2.1 Clock Specifications
      3. 7.10.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.10.3.1 Peripheral Description
        2. 7.10.3.2 MibSPI Transmit and Receive RAM Organization
          1. 7.10.3.2.1 SPI Timing Conditions
          2. 7.10.3.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-236 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-237 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-238
          3. 7.10.3.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-244 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-245 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-246
        3. 7.10.3.3 SPI Peripheral Mode I/O Timings
          1. 7.10.3.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-70 #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-71 #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-73
        4. 7.10.3.4 Typical Interface Protocol Diagram (Peripheral Mode)
      4. 7.10.4  LVDS Interface Configuration
        1. 7.10.4.1 LVDS Interface Timings
      5. 7.10.5  General-Purpose Input/Output
        1. 7.10.5.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      6. 7.10.6  Controller Area Network Interface (DCAN)
        1. 7.10.6.1 Dynamic Characteristics for the DCANx TX and RX Pins
      7. 7.10.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.10.7.1 Dynamic Characteristics for the CANx TX and RX Pins
      8. 7.10.8  Serial Communication Interface (SCI)
        1. 7.10.8.1 SCI Timing Requirements
      9. 7.10.9  Inter-Integrated Circuit Interface (I2C)
        1. 7.10.9.1 I2C Timing Requirements #GUID-36963FBF-DA1A-4FF8-B71D-4A185830E708/T4362547-185
      10. 7.10.10 Quad Serial Peripheral Interface (QSPI)
        1. 7.10.10.1 QSPI Timing Conditions
        2. 7.10.10.2 Timing Requirements for QSPI Input (Read) Timings #GUID-6DC69BBB-F187-4499-AC42-8C006552DEE1/T4362547-210 #GUID-6DC69BBB-F187-4499-AC42-8C006552DEE1/T4362547-209
        3. 7.10.10.3 QSPI Switching Characteristics
      11. 7.10.11 ETM Trace Interface
        1. 7.10.11.1 ETMTRACE Timing Conditions
        2. 7.10.11.2 ETM TRACE Switching Characteristics
      12. 7.10.12 Data Modification Module (DMM)
        1. 7.10.12.1 DMM Timing Requirements
      13. 7.10.13 JTAG Interface
        1. 7.10.13.1 JTAG Timing Conditions
        2. 7.10.13.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 7.10.13.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
      2. 8.3.2 Processor Subsystem
      3. 8.3.3 Host Interface
      4. 8.3.4 Main Subsystem Cortex-R4F Memory Map
      5. 8.3.5 DSP Subsystem Memory Map
      6. 8.3.6 Hardware Accelerator
    4. 8.4 Other Subsystems
      1. 8.4.1 ADC Channels (Service) for User Application
        1. 8.4.1.1 GP-ADC Parameter
  10. 9 Monitoring and Diagnostics
    1. 9.1 Monitoring and Diagnostic Mechanisms
      1. 9.1.1 Error Signaling Module
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2. 13.2 Tray Information for

12 Revision History

Changes from January 15, 2022 to September 11, 2024 (from Revision A (January 2022) to Revision B (September 2024))

  • (RF Specification): Updated Noise Figure, In-band P1dB vs Receiver GainGo

Changes from September 18, 2019 to January 15, 2022 (from Revision * (September 2019) to Revision A (January 2022))

  • Global: Datasheet updated to reflect Functional Safety-Compliance status of the mmWave device; Relevant Certification Collateral and details added Go
  • Global: Replaced "A2D" with "ADC"; Changed Masters Subsystem and Masters R4F to Main Subsystem and Main R4F; Shift to more inclusive langauge made in terms of Master/Slave terminologyGo
  • (Features) : Mentioned the specific operating temperature range for the mmWave SensorGo
  • (Device Information) : Functional Safety-Compliant OPNs for IWR1843 device updatedGo
  • Updated/Changed Functional Block Diagram for inclusive terminologyGo
  • (Device Comparison): Added a table-note to reflect Functional Safety-Compliance status of the device and LVDS Interface; Updated Product status for IWR6843 and IWR6843AOP devices from "AI" to "PD"Go
  • (Signal Descriptions): Added a NOTE on the GPIO state during power supply rampGo
  • (Signal Descriptions - Digital) : Added ADC_VALID, CHIRP_END, CHIRP_START, and FRAME_START SIGNAL NAME rowsGo
  • (Signal Description - Digital): Added missing DESCRIPTIONS to the EPWMxSYNC SIGNAL NAME rowsGo
  • (Signal Description - Digital) : Deleted BALL NO. "D14" from the EPWM1SYNCI rowGo
  • (Signal Descriptions) :Updated/Changed CLKP and CLKM descriptionsGo
  • (Pin Attributes (ABL0161 Package): Added the ADC_VALID, CHIRP_END, CHIRP_START, and FRAME_START signal names, modes, and type to each applicable BALL NUMBER.Go
  • (Absolute Maximum Ratings): Added entries for externally supplied power on the RF inputs (TX and RX) and a table-note for the signal level applied on TX.Go
  • (Maximum Current Ratings at Power Terminals): Updated the table-notes section to reflect typical supply voltage level conditions.Go
  • (Average Power Consumption at Power Terminals): Updated/Changed the typical average power numbersGo
  • (RF Specifications) : Added lead-in paragraph and "Noise Figure, In-band P1dB vs Receiver Gain" image.Go
  • (Clock Specifications): Updated/Changed Table 7-5 to reflect correct device operating temperature range.Go
  • (Table. External Clock Mode Specifications): Revised frequency tolerance specs from +/-50 to +/-100 ppmGo
  • Added a footnote for L3-Shared memory in DSP C674x Memory Map Go
  • (Monitoring and Diagnostic Mechanisms):Updated/modfied Monitoring and Diagnostics mechanisms for Functional Safety-Compliant IWR1843 deviceGo
  • (Reference Schematics) : Added weblinks to device EVM documentation collateral Go
  • (Device Nomenclature):Updated/changed Device Nomenclature Go