SWRS228B September   2019  – September 2024 IWR1843

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Signal Descriptions
      1. 6.2.1 Signal Descriptions - Digital
      2. 6.2.2 Signal Descriptions - Analog
    3. 6.3 Pin Attributes
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Supply Specifications
    6. 7.6  Power Consumption Summary
    7. 7.7  RF Specification
    8. 7.8  CPU Specifications
    9. 7.9  Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1  Power Supply Sequencing and Reset Timing
      2. 7.10.2  Input Clocks and Oscillators
        1. 7.10.2.1 Clock Specifications
      3. 7.10.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.10.3.1 Peripheral Description
        2. 7.10.3.2 MibSPI Transmit and Receive RAM Organization
          1. 7.10.3.2.1 SPI Timing Conditions
          2. 7.10.3.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-236 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-237 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-238
          3. 7.10.3.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-244 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-245 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-246
        3. 7.10.3.3 SPI Peripheral Mode I/O Timings
          1. 7.10.3.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-70 #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-71 #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-73
        4. 7.10.3.4 Typical Interface Protocol Diagram (Peripheral Mode)
      4. 7.10.4  LVDS Interface Configuration
        1. 7.10.4.1 LVDS Interface Timings
      5. 7.10.5  General-Purpose Input/Output
        1. 7.10.5.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      6. 7.10.6  Controller Area Network Interface (DCAN)
        1. 7.10.6.1 Dynamic Characteristics for the DCANx TX and RX Pins
      7. 7.10.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.10.7.1 Dynamic Characteristics for the CANx TX and RX Pins
      8. 7.10.8  Serial Communication Interface (SCI)
        1. 7.10.8.1 SCI Timing Requirements
      9. 7.10.9  Inter-Integrated Circuit Interface (I2C)
        1. 7.10.9.1 I2C Timing Requirements #GUID-36963FBF-DA1A-4FF8-B71D-4A185830E708/T4362547-185
      10. 7.10.10 Quad Serial Peripheral Interface (QSPI)
        1. 7.10.10.1 QSPI Timing Conditions
        2. 7.10.10.2 Timing Requirements for QSPI Input (Read) Timings #GUID-6DC69BBB-F187-4499-AC42-8C006552DEE1/T4362547-210 #GUID-6DC69BBB-F187-4499-AC42-8C006552DEE1/T4362547-209
        3. 7.10.10.3 QSPI Switching Characteristics
      11. 7.10.11 ETM Trace Interface
        1. 7.10.11.1 ETMTRACE Timing Conditions
        2. 7.10.11.2 ETM TRACE Switching Characteristics
      12. 7.10.12 Data Modification Module (DMM)
        1. 7.10.12.1 DMM Timing Requirements
      13. 7.10.13 JTAG Interface
        1. 7.10.13.1 JTAG Timing Conditions
        2. 7.10.13.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 7.10.13.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
      2. 8.3.2 Processor Subsystem
      3. 8.3.3 Host Interface
      4. 8.3.4 Main Subsystem Cortex-R4F Memory Map
      5. 8.3.5 DSP Subsystem Memory Map
      6. 8.3.6 Hardware Accelerator
    4. 8.4 Other Subsystems
      1. 8.4.1 ADC Channels (Service) for User Application
        1. 8.4.1.1 GP-ADC Parameter
  10. 9 Monitoring and Diagnostics
    1. 9.1 Monitoring and Diagnostic Mechanisms
      1. 9.1.1 Error Signaling Module
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2. 13.2 Tray Information for

6.2.1 Signal Descriptions - Digital

SIGNAL NAMEPIN TYPEDESCRIPTIONBALL NO.
ADC_VALIDOWhen high, indicating valid ADC samplesH13, J13, P13
BSS_UART_TXODebug UART Transmit [Radar Block]F14, H14, K13, N10, N13, N4, N5, R8
CAN_FD_RXICAN FD (MCAN) Receive SignalD13, F14, N10, N4, P12
CAN_FD_TXOCAN FD (MCAN) Transmit SignalE14, H14, N5, P10, R14
CAN_RXICAN (DCAN) Receive SignalE13
CAN_TXIOCAN (DCAN) Transmit SignalE15
CHIRP_ENDOPulse signal indicating the end of each chirpK13, N8, P9
CHIRP_STARTOPulse signal indicating the start of each chirpK13, N8, P9
DMM0IDebug Interface (Hardware In Loop) - Data LineR4
DMM1IDebug Interface (Hardware In Loop) - Data LineP5
DMM2IDebug Interface (Hardware In Loop) - Data LineR5
DMM3IDebug Interface (Hardware In Loop) - Data LineP6
DMM4IDebug Interface (Hardware In Loop) - Data LineR7
DMM5IDebug Interface (Hardware In Loop) - Data LineP7
DMM6IDebug Interface (Hardware In Loop) - Data LineR8
DMM7IDebug Interface (Hardware In Loop) - Data LineP8
DMM_CLKIDebug Interface (Hardware In Loop) - ClockN15
DMM_MUX_INIDebug Interface (Hardware In Loop) Mux Select between DMM1 and DMM2 (Two Instances)G13, J13, P4
DMM_SYNCIDebug Interface (Hardware In Loop) - SyncN14
DSS_UART_TXODebug UART Transmit [DSP]D13, E13, G14, P8, R12
EPWM1AOPWM Module 1 - Output AN5, N8
EPWM1BOPWM Module 1 - Output BH13, N5, P9
EPWM1SYNCIIPWM Module 1 - Sync Input J13
EPWM2AOPWM Module 2- Output AH13, N4, N5, P9
EPWM2BOPWM Module 2 - Output BN4
EPWM2SYNCOOPWM Module 2 - Sync OutputR7
EPWM3AOPWM Module 3 - Output AN4
EPWM3SYNCOOPWM Module 3 - Sync OutputP6
FRAME_STARTOPulse signal indicating the start of each frameK13, N8, P9
GPIO_0IOGeneral-purpose I/OH13
GPIO_1IOGeneral-purpose I/OJ13
GPIO_2IOGeneral-purpose I/OK13
GPIO_3IOGeneral-purpose I/OE13
GPIO_4IOGeneral-purpose I/OH14
GPIO_5IOGeneral-purpose I/OF14
GPIO_6IOGeneral-purpose I/OP11
GPIO_7IOGeneral-purpose I/OR12
GPIO_8IOGeneral-purpose I/OR13
GPIO_9IOGeneral-purpose I/ON12
GPIO_10IOGeneral-purpose I/OR14
GPIO_11IOGeneral-purpose I/OP12
GPIO_12IOGeneral-purpose I/OP13
GPIO_13IOGeneral-purpose I/OH13
GPIO_14IOGeneral-purpose I/ON5
GPIO_15IOGeneral-purpose I/ON4
GPIO_16IOGeneral-purpose I/OJ13
GPIO_17IOGeneral-purpose I/OP10
GPIO_18IOGeneral-purpose I/ON10
GPIO_19IOGeneral-purpose I/OD13
GPIO_20IOGeneral-purpose I/OE14
GPIO_21IOGeneral-purpose I/OF13
GPIO_22IOGeneral-purpose I/OG14
GPIO_23IOGeneral-purpose I/OR11
GPIO_24IOGeneral-purpose I/ON13
GPIO_25IOGeneral-purpose I/ON8
GPIO_26IOGeneral-purpose I/OK13
GPIO_27IOGeneral-purpose I/OP9
GPIO_28IOGeneral-purpose I/OP4
GPIO_29IOGeneral-purpose I/OG13
GPIO_30IOGeneral-purpose I/OE15
GPIO_31IOGeneral-purpose I/OR4
GPIO_32IOGeneral-purpose I/OP5
GPIO_33IOGeneral-purpose I/OR5
GPIO_34IOGeneral-purpose I/OP6
GPIO_35IOGeneral-purpose I/OR7
GPIO_36IOGeneral-purpose I/OP7
GPIO_37IOGeneral-purpose I/OR8
GPIO_38IOGeneral-purpose I/OP8
GPIO_47IOGeneral-purpose I/ON15
I2C_SCLIOI2C ClockG14, N4
I2C_SDAIOI2C DataF13, N5
LVDS_TXP[0]ODifferential data Out – Lane 0J14
LVDS_TXM[0]OJ15
LVDS_TXP[1]ODifferential data Out – Lane 1K14
LVDS_TXM[1]OK15
LVDS_CLKPODifferential clock OutL14
LVDS_CLKMOL15
LVDS_FRCLKPODifferential Frame ClockM14
LVDS_FRCLKMOM15
MCU_CLKOUTOProgrammable clock given out to external MCU or the processorN8
MSS_UARTA_RXIMain Subsystem - UART A ReceiveF14, N4, R11
MSS_UARTA_TXOMain Subsystem - UART A TransmitH14, N13, N5, R4
MSS_UARTB_RXIOMain Subsystem - UART B ReceiveN4, P4
MSS_UARTB_TXOMain Subsystem - UART B TransmitF14, H14, K13, N13, N5, P10, P7
NDMM_ENIDebug Interface (Hardware In Loop) Enable - Active Low SignalN13, N5
NERROR_INIFailsafe input to the device. Nerror output from any other device can be concentrated in the error signaling monitor module inside the device and appropriate action can be taken by FirmwareN7
NERROR_OUTOOpen drain fail safe output signal. Connected to PMIC/Processor/MCU to indicate that some severe criticality fault has happened. Recovery would be through reset.N6
PMIC_CLKOUTOOutput Clock from IWR1843 device for PMICH13, K13, P9
QSPI[0]IOQSPI Data Line #0 (Used with Serial Data Flash)R13
QSPI[1]IOQSPI Data Line #1 (Used with Serial Data Flash)N12
QSPI[2]IQSPI Data Line #2 (Used with Serial Data Flash)R14
QSPI[3]IOQSPI Data Line #3 (Used with Serial Data Flash)P12
QSPI_CLKIOQSPI Clock (Used with Serial Data Flash)R12
QSPI_CLK_EXTIQSPI Clock (Used with Serial Data Flash)H14
QSPI_CS_NIOQSPI Chip Select (Used with Serial Data Flash)P11
RS232_RXIDebug UART (Operates as Bus Main) - Receive SignalN4
RS232_TXODebug UART (Operates as Bus Main) - Transmit SignalN5
SOP[0]ISense On Power - Line#0N13
SOP[1]ISense On Power - Line#1G13
SOP[2]ISense On Power - Line#2P9
SPIA_CLKIOSPI Channel A - ClockE13
SPIA_CS_NIOSPI Channel A - Chip SelectE15
SPIA_MISOIOSPI Channel A - Main In Slave OutE14
SPIA_MOSIIOSPI Channel A - Main Out Slave InD13
SPIB_CLKIOSPI Channel B - ClockF14, R12
SPIB_CS_NIOSPI Channel B Chip Select (Instance ID 0)H14, P11
SPIB_CS_N_1IOSPI Channel B Chip Select (Instance ID 1)G13, J13, P13
SPIB_CS_N_2IOSPI Channel B Chip Select (Instance ID 2)G13, J13, N12
SPIB_MISOIOSPI Channel B - Main In Slave OutG14, R13
SPIB_MOSIIOSPI Channel B - Main Out Slave InF13, N12
SPI_HOST_INTROOut of Band Interrupt to an external host communicating over SPIP13
SYNC_INILow frequency Synchronization signal inputP4
SYNC_OUTOLow Frequency Synchronization Signal outputG13, J13, K13, P4
TCKIJTAG Test ClockP10
TDIIJTAG Test Data InputR11
TDOOJTAG Test Data OutputN13
TMSIJTAG Test Mode SignalN10
TRACE_CLKODebug Trace Output - ClockN15
TRACE_CTLODebug Trace Output - ControlN14
TRACE_DATA_0ODebug Trace Output - Data LineR4
TRACE_DATA_1ODebug Trace Output - Data LineP5
TRACE_DATA_2ODebug Trace Output - Data LineR5
TRACE_DATA_3ODebug Trace Output - Data LineP6
TRACE_DATA_4ODebug Trace Output - Data LineR7
TRACE_DATA_5ODebug Trace Output - Data LineP7
TRACE_DATA_6ODebug Trace Output - Data LineR8
TRACE_DATA_7ODebug Trace Output - Data LineP8
WARM_RESETIOOpen drain fail safe warm reset signal. Can be driven from PMIC for diagnostic or can be used as status signal that the device is going through reset.N9