SWRS228B September   2019  – September 2024 IWR1843

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Signal Descriptions
      1. 6.2.1 Signal Descriptions - Digital
      2. 6.2.2 Signal Descriptions - Analog
    3. 6.3 Pin Attributes
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Supply Specifications
    6. 7.6  Power Consumption Summary
    7. 7.7  RF Specification
    8. 7.8  CPU Specifications
    9. 7.9  Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1  Power Supply Sequencing and Reset Timing
      2. 7.10.2  Input Clocks and Oscillators
        1. 7.10.2.1 Clock Specifications
      3. 7.10.3  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 7.10.3.1 Peripheral Description
        2. 7.10.3.2 MibSPI Transmit and Receive RAM Organization
          1. 7.10.3.2.1 SPI Timing Conditions
          2. 7.10.3.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-236 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-237 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-238
          3. 7.10.3.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-244 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-245 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-246
        3. 7.10.3.3 SPI Peripheral Mode I/O Timings
          1. 7.10.3.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-70 #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-71 #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-73
        4. 7.10.3.4 Typical Interface Protocol Diagram (Peripheral Mode)
      4. 7.10.4  LVDS Interface Configuration
        1. 7.10.4.1 LVDS Interface Timings
      5. 7.10.5  General-Purpose Input/Output
        1. 7.10.5.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      6. 7.10.6  Controller Area Network Interface (DCAN)
        1. 7.10.6.1 Dynamic Characteristics for the DCANx TX and RX Pins
      7. 7.10.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 7.10.7.1 Dynamic Characteristics for the CANx TX and RX Pins
      8. 7.10.8  Serial Communication Interface (SCI)
        1. 7.10.8.1 SCI Timing Requirements
      9. 7.10.9  Inter-Integrated Circuit Interface (I2C)
        1. 7.10.9.1 I2C Timing Requirements #GUID-36963FBF-DA1A-4FF8-B71D-4A185830E708/T4362547-185
      10. 7.10.10 Quad Serial Peripheral Interface (QSPI)
        1. 7.10.10.1 QSPI Timing Conditions
        2. 7.10.10.2 Timing Requirements for QSPI Input (Read) Timings #GUID-6DC69BBB-F187-4499-AC42-8C006552DEE1/T4362547-210 #GUID-6DC69BBB-F187-4499-AC42-8C006552DEE1/T4362547-209
        3. 7.10.10.3 QSPI Switching Characteristics
      11. 7.10.11 ETM Trace Interface
        1. 7.10.11.1 ETMTRACE Timing Conditions
        2. 7.10.11.2 ETM TRACE Switching Characteristics
      12. 7.10.12 Data Modification Module (DMM)
        1. 7.10.12.1 DMM Timing Requirements
      13. 7.10.13 JTAG Interface
        1. 7.10.13.1 JTAG Timing Conditions
        2. 7.10.13.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 7.10.13.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Subsystems
      1. 8.3.1 RF and Analog Subsystem
        1. 8.3.1.1 Clock Subsystem
        2. 8.3.1.2 Transmit Subsystem
        3. 8.3.1.3 Receive Subsystem
      2. 8.3.2 Processor Subsystem
      3. 8.3.3 Host Interface
      4. 8.3.4 Main Subsystem Cortex-R4F Memory Map
      5. 8.3.5 DSP Subsystem Memory Map
      6. 8.3.6 Hardware Accelerator
    4. 8.4 Other Subsystems
      1. 8.4.1 ADC Channels (Service) for User Application
        1. 8.4.1.1 GP-ADC Parameter
  10. 9 Monitoring and Diagnostics
    1. 9.1 Monitoring and Diagnostic Mechanisms
      1. 9.1.1 Error Signaling Module
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2. 13.2 Tray Information for
7.10.3.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output,
SPISIMO = output, and SPISOMI = input)(1)(2)(3)
NO.PARAMETERMINTYPMAXUNIT
1tc(SPC)MCycle time, SPICLK(4)25256tc(VCLK)ns
2(4)tw(SPCH)MPulse duration, SPICLK high (clock polarity = 0)0.5tc(SPC)M – 40.5tc(SPC)M + 4ns
tw(SPCL)MPulse duration, SPICLK low (clock polarity = 1)0.5tc(SPC)M – 40.5tc(SPC)M + 4
3(4)tw(SPCL)MPulse duration, SPICLK low (clock polarity = 0)0.5tc(SPC)M – 40.5tc(SPC)M + 4ns
tw(SPCH)MPulse duration, SPICLK high (clock polarity = 1)0.5tc(SPC)M – 40.5tc(SPC)M + 4
4(4)td(SPCH-SIMO)MDelay time, SPISIMO valid before SPICLK low, (clock polarity = 0)0.5tc(SPC)M – 3ns
td(SPCL-SIMO)MDelay time, SPISIMO valid before SPICLK high, (clock polarity = 1)0.5tc(SPC)M – 3
5(4)tv(SPCL-SIMO)MValid time, SPISIMO data valid after SPICLK low, (clock polarity = 0)0.5tc(SPC)M – 10.5ns
tv(SPCH-SIMO)MValid time, SPISIMO data valid after SPICLK high, (clock polarity = 1)0.5tc(SPC)M – 10.5
6(5)tC2TDELAYSetup time CS active until SPICLK high
(clock polarity = 0)		CSHOLD = 0(C2TDELAY+2)*tc(VCLK) – 7.5(C2TDELAY+2) * tc(VCLK) + 7ns
CSHOLD = 1(C2TDELAY +3) * tc(VCLK) – 7.5(C2TDELAY+3) * tc(VCLK) + 7
Setup time CS active until SPICLK low
(clock polarity = 1)		CSHOLD = 0(C2TDELAY+2)*tc(VCLK) – 7.5(C2TDELAY+2) * tc(VCLK) + 7
CSHOLD = 1(C2TDELAY +3) * tc(VCLK) – 7.5(C2TDELAY+3) * tc(VCLK) + 7
7(5)tT2CDELAYHold time, SPICLK low until CS inactive (clock polarity = 0)0.5*tc(SPC)M + (T2CDELAY + 1) *tc(VCLK) – 70.5*tc(SPC)M + (T2CDELAY + 1) * tc(VCLK) + 7.5ns
Hold time, SPICLK high until CS inactive (clock polarity = 1)0.5*tc(SPC)M + (T2CDELAY + 1) *tc(VCLK) – 70.5*tc(SPC)M + (T2CDELAY + 1) * tc(VCLK) + 7.5
8(4)tsu(SOMI-SPCL)MSetup time, SPISOMI before SPICLK low
(clock polarity = 0)		5ns
tsu(SOMI-SPCH)MSetup time, SPISOMI before SPICLK high
(clock polarity = 1)		5
9(4)th(SPCL-SOMI)MHold time, SPISOMI data valid after SPICLK low
(clock polarity = 0)		3ns
th(SPCH-SOMI)MHold time, SPISOMI data valid after SPICLK high
(clock polarity = 1)		3
(1) The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared (where x= 0 or 1).
(2) tc(MSS_VCLK) = main subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.
(3) When the SPI is in Controller mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(MSS_VCLK) ≥ 25ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits. For PS values of 0: tc(SPC)M = 2tc(MSS_VCLK) ≥ 25ns.
(4) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(5) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
IWR1843 SPI Controller Mode External Timing (CLOCK PHASE = 0)Figure 7-4 SPI Controller Mode External Timing (CLOCK PHASE = 0)
IWR1843 SPI Controller Mode Chip Select Timing (CLOCK PHASE = 0)Figure 7-5 SPI Controller Mode Chip Select Timing (CLOCK PHASE = 0)