SWRS236C March   2021  – January 2024 AWR1843AOP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions
      1. 5.3.1 Pin Functions - Digital and Analog [ALP Package]
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Power-On Hours (POH)
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Power Supply Specifications
    6. 6.6  Power Consumption Summary
    7. 6.7  RF Specification
    8. 6.8  CPU Specifications
    9. 6.9  Thermal Resistance Characteristics for FCBGA Package [ALP0180A]
    10. 6.10 Timing and Switching Characteristics
      1. 6.10.1  Antenna Radiation Patterns
        1. 6.10.1.1 Antenna Radiation Patterns for Receiver
        2. 6.10.1.2 Antenna Radiation Patterns for Transmitter
      2. 6.10.2  Antenna Positions
      3. 6.10.3  Power Supply Sequencing and Reset Timing
      4. 6.10.4  Input Clocks and Oscillators
        1. 6.10.4.1 Clock Specifications
      5. 6.10.5  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 6.10.5.1 Peripheral Description
        2. 6.10.5.2 MibSPI Transmit and Receive RAM Organization
          1. 6.10.5.2.1 SPI Timing Conditions
          2. 6.10.5.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. 6.10.5.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 6.10.5.3 SPI Peripheral Mode I/O Timings
          1. 6.10.5.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        4. 6.10.5.4 Typical Interface Protocol Diagram (Slave Mode)
      6. 6.10.6  LVDS Interface Configuration
        1. 6.10.6.1 LVDS Interface Timings
      7. 6.10.7  General-Purpose Input/Output
        1. 6.10.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) #GUID-4685AB93-A014-47EA-9F05-952FFC28DBFA/T4362547-45 #GUID-4685AB93-A014-47EA-9F05-952FFC28DBFA/T4362547-50
      8. 6.10.8  Controller Area Network Interface (DCAN)
        1. 6.10.8.1 Dynamic Characteristics for the DCANx TX and RX Pins
      9. 6.10.9  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 6.10.9.1 Dynamic Characteristics for the CANx TX and RX Pins
      10. 6.10.10 Serial Communication Interface (SCI)
        1. 6.10.10.1 SCI Timing Requirements
      11. 6.10.11 Inter-Integrated Circuit Interface (I2C)
        1. 6.10.11.1 I2C Timing Requirements #GUID-64613E7E-5DDF-4B01-8FA0-13739060F368/T4362547-185
      12. 6.10.12 Quad Serial Peripheral Interface (QSPI)
        1. 6.10.12.1 QSPI Timing Conditions
        2. 6.10.12.2 Timing Requirements for QSPI Input (Read) Timings #GUID-6A95C194-2C40-46FE-9793-4574200DA2C4/T4362547-210 #GUID-6A95C194-2C40-46FE-9793-4574200DA2C4/T4362547-209
        3. 6.10.12.3 QSPI Switching Characteristics
      13. 6.10.13 ETM Trace Interface
        1. 6.10.13.1 ETMTRACE Timing Conditions
        2. 6.10.13.2 ETM TRACE Switching Characteristics
      14. 6.10.14 Data Modification Module (DMM)
        1. 6.10.14.1 DMM Timing Requirements
      15. 6.10.15 JTAG Interface
        1. 6.10.15.1 JTAG Timing Conditions
        2. 6.10.15.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 6.10.15.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Subsystems
      1. 7.3.1 RF and Analog Subsystem
        1. 7.3.1.1 Clock Subsystem
        2. 7.3.1.2 Transmit Subsystem
        3. 7.3.1.3 Receive Subsystem
      2. 7.3.2 Processor Subsystem
      3. 7.3.3 Automotive Interface
      4. 7.3.4 Main Subsystem Cortex-R4F Memory Map
      5. 7.3.5 DSP Subsystem Memory Map
    4. 7.4 Other Subsystems
      1. 7.4.1 ADC Channels (Service) for User Application
        1. 7.4.1.1 GP-ADC Parameter
  9. 8 Monitoring and Diagnostics
    1. 8.1 Monitoring and Diagnostic Mechanisms
      1. 8.1.1 Error Signaling Module
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Application Information
    2. 9.2 Reference Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

5.3.1 Pin Functions - Digital and Analog [ALP Package]

Table 5-4 lists the pins by function and describes that function.

 

Table 5-4 Pin Functions - Digital and Analog [ALP Package]
NAME I/O DESCRIPTION NO.
DIGITAL
BSS_UART_TX O Debug UART Transmit [Radar Block] D3, E2, K3, L2, U8, U10, U16, V16
CAN_FD_RX I CAN FD (MCAN) Receive Signal A4, B3, E2, F2, K2, U8, V16
CAN_FD_TX O CAN FD (MCAN) Transmit Signal B4, C3, D1, D3, J3, T3, U16
CAN_RX CAN (DCAN) Receive Signal D2
CAN_TX CAN (DCAN) Transmit Signal C2
DMM0 I Debug Interface (Hardware In Loop) - Data Line U7
DMM1 I Debug Interface (Hardware In Loop) - Data Line U6
DMM2 I Debug Interface (Hardware In Loop) - Data Line V5
DMM3 I Debug Interface (Hardware In Loop) - Data Line U5
DMM4 I Debug Interface (Hardware In Loop) - Data Line V3
DMM5 I Debug Interface (Hardware In Loop) - Data Line M1
DMM6 I Debug Interface (Hardware In Loop) - Data Line L2
DMM7 I Debug Interface (Hardware In Loop) - Data Line L1
DMM8 I Debug Interface (Hardware In Loop) - Data Line C3
DMM9 I Debug Interface (Hardware In Loop) - Data Line B3
DMM10 I Debug Interface (Hardware In Loop) - Data Line C4
DMM11 I Debug Interface (Hardware In Loop) - Data Line A3
DMM12 I Debug Interface (Hardware In Loop) - Data Line B4
DMM13 I Debug Interface (Hardware In Loop) - Data Line A4
DMM14 I Debug Interface (Hardware In Loop) - Data Line C5
DMM15 I Debug Interface (Hardware In Loop) - Data Line B5
DMM_CLK I Debug Interface (Hardware In Loop) - Clock U3
DMM_MUX_IN I Debug Interface (Hardware In Loop) Mux Select between DMM1 and DMM2 (Two Instances) L3, M3, U12
DMM_SYNC I Debug Interface (Hardware In Loop) - Sync U4
DSS_UART_TX O Debug UART Transmit [DSP] D2, F2, G3, H2, L1
EPWM1A O PWM Module 1 - Output A B4, U16, V13
EPWM1B O PWM Module 1 - Output B A4, M2, U16, V10
EPWM1SYNCI I PWM Module 1 - Sync Input C3, L3
EPWM1SYNCO I PWM Module 1 - Sync Output B3
EPWM2A O PWM Module 2- Output A C5, M2, U16, V10, V16
EPWM2B O PWM Module 2 - Output B B5, V16
EPWM2SYNCO O PWM Module 2 - Sync Output V3
EPWM3A O PWM Module 3 - Output A C4, V16
EPWM3B O PWM Module 3 - Output A A3
EPWM3SYNCO O PWM Module 3 - Sync Output U5
GPIO_0 IO General-purpose I/O M2
GPIO_1 IO General-purpose I/O L3
GPIO_2 IO General-purpose I/O K3
GPIO_3 IO General-purpose I/O D2
GPIO_4 IO General-purpose I/O D3
GPIO_5 IO General-purpose I/O E2
GPIO_6 IO General-purpose I/O J2
GPIO_7 IO General-purpose I/O H2
GPIO_8 IO General-purpose I/O H3
GPIO_9 IO General-purpose I/O G2
GPIO_10 IO General-purpose I/O J3
GPIO_11 IO General-purpose I/O K2
GPIO_12 IO General-purpose I/O B2
GPIO_13 IO General-purpose I/O M2
GPIO_14 IO General-purpose I/O U16
GPIO_15 IO General-purpose I/O V16
GPIO_16 IO General-purpose I/O L3
GPIO_17 IO General-purpose I/O T3
GPIO_18 IO General-purpose I/O U8
GPIO_19 IO General-purpose I/O F2
GPIO_20 IO General-purpose I/O D1
GPIO_21 IO General-purpose I/O G1
GPIO_22 IO General-purpose I/O G3
GPIO_23 IO General-purpose I/O U9
GPIO_24 IO General-purpose I/O U10
GPIO_25 IO General-purpose I/O V13
GPIO_26 IO General-purpose I/O K3
GPIO_27 IO General-purpose I/O V10
GPIO_28 IO General-purpose I/O U12
GPIO_29 IO General-purpose I/O M3
GPIO_30 IO General-purpose I/O C2, D2
GPIO_31 IO General-purpose I/O U7
GPIO_32 IO General-purpose I/O U6
GPIO_33 IO General-purpose I/O V5
GPIO_34 IO General-purpose I/O U5
GPIO_35 IO General-purpose I/O V3
GPIO_36 IO General-purpose I/O M1
GPIO_37 IO General-purpose I/O L2
GPIO_38 IO General-purpose I/O L1
GPIO_39 IO General-purpose I/O C3
GPIO_40 IO General-purpose I/O B3
GPIO_41 IO General-purpose I/O C4
GPIO_42 IO General-purpose I/O A3
GPIO_43 IO General-purpose I/O B4
GPIO_44 IO General-purpose I/O A4
GPIO_45 IO General-purpose I/O C5
GPIO_46 IO General-purpose I/O B5
GPIO_47 IO General-purpose I/O U3
I2C_SCL IO I2C Clock G3, V16
I2C_SDA IO I2C Data G1, U16
LVDS_TXP[0] O Differential data Out – Lane 0 N2
LVDS_TXM[0] O Differential data Out – Lane 0 N1
LVDS_TXP[1] O Differential data Out – Lane 1 P2
LVDS_TXM[1] O Differential data Out – Lane 1 P1
LVDS_CLKP O Differential clock Out R1
LVDS_CLKM O Differential clock Out R2
LVDS_FRCLKP O Differential Frame Clock T1
LVDS_FRCLKM O Differential Frame Clock T2
MCU_CLKOUT O Programmable clock given out to external MCU or the processor V13
MSS_UARTA_RX I Main Subsystem - UART A Receive E2, U9, V16
MSS_UARTA_TX O Main Subsystem - UART A Transmit D3, U7, U10, U16
MSS_UARTB_RX IO Main Subsystem - UART B Receive U12, V16
MSS_UARTB_TX O Main Subsystem - UART B Transmit D3, E2, K3, M1, T3, U10, U16
NDMM_EN I Debug Interface (Hardware In Loop) Enable - Active Low Signal U10, U16
NERROR_IN I Failsafe input to the device. Nerror output from any other device can be concentrated in the error signaling monitor module inside the device and appropriate action can be taken by Firmware U14
NERROR_OUT O Open drain fail safe output signal. Connected to PMIC/Processor/MCU to indicate that some severe criticality fault has happened. Recovery would be through reset. U15
PMIC_CLKOUT O Output Clock from AWR6843AOP device for PMIC K3, M2, V10
QSPI[0] IO QSPI Data Line #0 (Used with Serial Data Flash) H3
QSPI[1] I QSPI Data Line #1 (Used with Serial Data Flash) G2
QSPI[2] I QSPI Data Line #2 (Used with Serial Data Flash) J3
QSPI[3] I QSPI Data Line #3 (Used with Serial Data Flash) K2
QSPI_CLK O QSPI Clock (Used with Serial Data Flash) H2
QSPI_CLK_EXT I QSPI Clock (Used with Serial Data Flash) D3
QSPI_CS_N O QSPI Chip Select (Used with Serial Data Flash) J2
RS232_RX I Debug UART (Operates as Bus Master) - Receive Signal V16
RS232_TX O Debug UART (Operates as Bus Master) - Transmit Signal U16
SOP[0] I Sense On Power - Line#0 U10
SOP[1] I Sense On Power - Line#1 M3
SOP[2] I Sense On Power - Line#2 V10
SPIA_CLK IO SPI Channel A - Clock D2
SPIA_CS_N IO SPI Channel A - Chip Select C2
SPIA_MISO IO SPI Channel A - Master In Slave Out D1
SPIA_MOSI IO SPI Channel A - Master Out Slave In F2
SPIB_CLK IO SPI Channel B - Clock E2, H2
SPIB_CS_N IO SPI Channel B Chip Select (Instance ID 0) D3, J2
SPIB_CS_N_1 IO SPI Channel B Chip Select (Instance ID 1) B2, L3, M3
SPIB_CS_N_2 IO SPI Channel B Chip Select (Instance ID 2) G2, L3, M3
SPIB_MISO IO SPI Channel B - Master In Slave Out G3, H3
SPIB_MOSI IO SPI Channel B - Master Out Slave In G1, G2
SPI_HOST_INTR O Out of Band Interrupt to an external host communicating over SPI B2
SYNC_IN I Low frequency Synchronization signal input U12
SYNC_OUT O Low Frequency Synchronization Signal output K3, L3, M3, U12
TCK I JTAG Test Clock T3
TDI I JTAG Test Data Input U9
TDO O JTAG Test Data Output U10
TMS I JTAG Test Mode Signal U8
TRACE_CLK O Debug Trace Output - Clock U3
TRACE_CTL O Debug Trace Output - Control U4
TRACE_DATA_0 O Debug Trace Output - Data Line U7
TRACE_DATA_1 O Debug Trace Output - Data Line U6
TRACE_DATA_2 O Debug Trace Output - Data Line V5
TRACE_DATA_3 O Debug Trace Output - Data Line U5
TRACE_DATA_4 O Debug Trace Output - Data Line V3
TRACE_DATA_5 O Debug Trace Output - Data Line M1
TRACE_DATA_6 O Debug Trace Output - Data Line L2
TRACE_DATA_7 O Debug Trace Output - Data Line L1
TRACE_DATA_8 O Debug Trace Output - Data Line C3
TRACE_DATA_9 O Debug Trace Output - Data Line B3
TRACE_DATA_10 O Debug Trace Output - Data Line C4
TRACE_DATA_11 O Debug Trace Output - Data Line A3
TRACE_DATA_12 O Debug Trace Output - Data Line B4
TRACE_DATA_13 O Debug Trace Output - Data Line A4
TRACE_DATA_14 O Debug Trace Output - Data Line C5
TRACE_DATA_15 O Debug Trace Output - Data Line B5
FRAME_START O Pulse signal indicating the start of each frame K3, V10, V13
CHIRP_START O Pulse signal indicating the start of each chirp K3, V10, V13
CHIRP_END O Pulse signal indicating the end of each chirp K3, V10, V13
ADC_VALID O When high, indicating valid ADC samples B2, L3, M2
WARM_RESET IO Open drain fail safe warm reset signal. Can be driven from PMIC for diagnostic or can be used as status signal that the device is going through reset. U13
ANALOG
NRESET I Power on reset for chip. Active low U11
CLKP I In XTAL mode: Differential port for reference crystal In External clock mode: Single ended input reference clock port A7
CLKM I In XTAL mode: Differential port for reference crystal In External clock mode: Connect this port to ground B7
OSC_CLKOUT O Reference clock output from clocking sub system after cleanup PLL (1.4-V output voltage swing). A14, K3
VBGAP O Device's Band Gap Reference Output A16
VDDIN Power 1.2V digital power supply E1, J1, V4, V8, V15
VIN_SRAM Power 1.2V power rail for internal SRAM A5, V6, V12
VNWA Power 1.2V power rail for SRAM array back bias C1, V7, V14
VIOIN Power I/O Supply (3.3V or 1.8V): All CMOS I/Os would operate on this supply H1, V9
VIOIN_18 Power 1.8V supply for CMOS IO B1, F1, K1, V11
VIN_18CLK Power 1.8V supply for clock module C15, C18
VIOIN_18DIFF Power 1.8V supply for LVDS port U2
VPP Power Voltage supply for fuse chain V2
VIN_13RF1 Power 1.3V Analog and RF supply,VIN_13RF1 and VIN_13RF2 could be shorted on the board J16, J17, J18
VIN_13RF2 Power 1.3V Analog and RF supply H16, H17, H18
VIN_18BB Power 1.8V Analog base band power supply M16, M17, M18
VIN_18VCO Power 1.8V RF VCO supply A12, C11
VSS Ground Digital ground A1, A2, E3, F3, N3, P3, R3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, U1, V1
VSSA Ground Analog ground A6, A8, A11, A13, A15, A17, A18, B6, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18, C6, C7, C8, C12, C13, C14, C16, C17, D16, D17, D18, E16, E17, E18, F16, F17, F18, K16, K17, K18, L16, L17, L18, N16, N17, N18, P16, R16, R17, T17, U17, U18, V17, V18
VOUT_14APLL O Internal LDO output A10
VOUT_14SYNTH O Internal LDO output A9
VOUT_PA IO Internal LDO output G16, G17, G18
Analog Test1 / GPADC1 IO Analog IO dedicated for ADC service P18
Analog Test2 / GPADC2 IO Analog IO dedicated for ADC service P17
Analog Test3 / GPADC3 IO Analog IO dedicated for ADC service R18
Analog Test4 / GPADC4 IO Analog IO dedicated for ADC service T18
ANAMUX / GPADC5 IO Analog IO dedicated for ADC service C9
VSENSE / GPADC6 IO Analog IO dedicated for ADC service C10