The AWR6843AOP is an Antenna-on-Package (AOP) device that is an evolution within the single-chip radar device family from Texas Instruments (TI). This device enables unprecedented levels of integration in an extremely small form factor and is an ideal solution for low power, self-monitored, ultra-accurate radar systems in the Automtive space.Multiple automotive qualified variants are currently available including Functional Safety-Compliant devices (ASIL-B) and non-functional safety devices.
It integrates a DSP subsystem, which contains TI's high-performance C674x DSP for the Radar Signal processing. The device includes a BIST processor subsystem, which is responsible for radio configuration, control, and calibration. Additionally, the device includes a user programmable Arm Cortex-R4F based for automotive interfacing. The Hardware Accelerator block (HWA) can perform radar processing and can offload the DSP in order to execute higher level algorithms. Simple programming model changes can enable a wide variety of sensor applications with the possibility of dynamic reconfiguration for implementing a multimode sensor. Additionally, the device is provided as a complete platform solution including reference hardware design, software drivers, sample configurations, API guide, and user documentation.
PART NUMBER | PACKAGE(1) | BODY SIZE | TRAY / TAPE AND REEL |
---|---|---|---|
AWR6843ARBGALPQ1 | FCBGA (180) | 15 mm × 15 mm | Tray |
AWR6843ARBGALPRQ1 | FCBGA (180) | 15 mm × 15 mm | Tape and Reel |
AWR6843ARBSALPQ1 | FCBGA (180) | 15 mm × 15 mm | Tray |
AWR6843ARBSALPRQ1 | FCBGA (180) | 15 mm × 15 mm | Tape and Reel |
Figure 4-1 shows the functional block diagram of the device.
Changes from November 13, 2020 to May 27, 2021 (from Revision * (November 2020) to Revision A (May 2021))
Changes from May 28, 2021 to June 1, 2021 (from Revision A (May 2021) to Revision B (June 2021))
Changes from June 2, 2021 to July 31, 2022 (from Revision B (June 2021) to Revision C (July 2022))
FUNCTION | AWR6843AOP(1) | AWR1843AOP | AWR6843 | AWR6443 | AWR1843 | AWR1642 | AWR1443 | |
---|---|---|---|---|---|---|---|---|
Antenna on Package (AOP) | Yes | Yes | — | — | — | — | — | |
Number of receivers | 4 | 4 | 4 | 4 | 4 | 4 | 4 | |
Number of transmitters | 3(2) | 3(2) | 3(2) | 3(2) | 3(2) | 2 | 3 | |
RF frequency range | 60 to 64 GHz | 76 to 81 GHz | 60 to 64 GHz | 60 to 64 GHz | 76 to 81 GHz | 76 to 81 GHz | 76 to 81 GHz | |
On-chip memory | 1.75MB | 2MB | 1.75MB | 1.4MB | 2MB | 1.5MB | 576KB | |
Max I/F (Intermediate Frequency) (MHz) | 10 | 10 | 10 | 10 | 10 | 5 | 5 | |
Max real sampling rate (Msps) | 25 | 25 | 25 | 25 | 25 | 12.5 | 12.5 | |
Max complex sampling rate (Msps) | 12.5 | 12.5 | 12.5 | 12.5 | 12.5 | 6.25 | 6.25 | |
Device Security(3) | Yes | Yes | Yes | — | Yes | Yes | — | |
Processors | ||||||||
MCU (R4F) | Yes | Yes | Yes | Yes | Yes | Yes | Yes | |
DSP (C674x) | Yes | Yes | Yes | — | Yes | Yes | — | |
Peripherals | ||||||||
Serial Peripheral Interface (SPI) ports | 2 | 2 | 2 | 2 | 2 | 2 | 1 | |
Quad Serial Peripheral Interface (QSPI) | Yes | Yes | Yes | Yes | Yes | Yes | Yes | |
Inter-Integrated Circuit (I2C) interface | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Controller Area Network (DCAN) interface | — | 1 | — | — | 1 | 1 | 1 | |
Controller Area Network (CAN-FD) interface | 2 | 1 | 2 | 2 | 1 | — | — | |
Trace | Yes | Yes | Yes | Yes | Yes | Yes | — | |
PWM | Yes | Yes | Yes | Yes | Yes | Yes | — | |
Hardware In Loop (HIL/DMM) | Yes | Yes | Yes | Yes | Yes | Yes | — | |
GPADC | Yes | Yes | Yes | Yes | Yes | Yes | Yes | |
LVDS/Debug(4) | Yes | Yes | Yes | Yes | Yes | Yes | Yes | |
CSI2 | — | — | — | — | — | — | — | |
Hardware accelerator | Yes | Yes | Yes | Yes | Yes | — | Yes | |
1-V bypass mode | Yes | Yes | Yes | Yes | Yes | Yes | Yes | |
JTAG | Yes | Yes | Yes | Yes | Yes | Yes | Yes | |
Product status | Product Preview
(PP), Advance Information (AI), or Production Data (PD) |
PD(5) | PD(5) | PD(5) | PD(5) | PD(5) | PD(5) | PD(5) |
For information about other devices in this family of products or related products see the links that follow.
Figure 7-1 shows the pin locations for the 180-pin 15 × 15 mm FCBGA package
All IO pins of the device (except NERROR IN, NERROR_OUT, and WARM_RESET) are non-failsafe; hence, care needs to be taken that they are not driven externally without the VIO supply being present to the device.
The GPIO state during the power supply ramp is not ensured. In case the GPIO is used in the application where the state of the GPIO is critical, even when NRESET is low , a tri-state buffer should be used to isolate the GPIO output from the radar device and a pull resister used to define the required state in the application. The NRESET signal to the radar device could be used to control the output enable (OE) of the tri-state buffer.
NAME | I/O | DESCRIPTION | NO. |
---|---|---|---|
DIGITAL | |||
BSS_UART_TX | O | Debug UART Transmit [Radar Block] | D3, E2, K3, L2, U8, U10, U16, V16 |
CAN1_FD_RX | I | CAN1 FD (MCAN) Receive Signal | A4, B3, E2, F2, K2, U8, V16 |
CAN1_FD_TX | O | CAN1 FD (MCAN) Transmit Signal | C2, C3, D1, D3, J3, T3, U16 |
CAN2_FD_RX | I | CAN2 FD (MCAN) Receive Signal | D2 |
CAN2_FD_TX | O | CAN2 FD (MCAN) Transmit Signal | B4 |
DMM0 | I | Debug Interface (Hardware In Loop) - Data Line | U7 |
DMM1 | I | Debug Interface (Hardware In Loop) - Data Line | U6 |
DMM2 | I | Debug Interface (Hardware In Loop) - Data Line | V5 |
DMM3 | I | Debug Interface (Hardware In Loop) - Data Line | U5 |
DMM4 | I | Debug Interface (Hardware In Loop) - Data Line | V3 |
DMM5 | I | Debug Interface (Hardware In Loop) - Data Line | M1 |
DMM6 | I | Debug Interface (Hardware In Loop) - Data Line | L2 |
DMM7 | I | Debug Interface (Hardware In Loop) - Data Line | L1 |
DMM8 | I | Debug Interface (Hardware In Loop) - Data Line | C3 |
DMM9 | I | Debug Interface (Hardware In Loop) - Data Line | B3 |
DMM10 | I | Debug Interface (Hardware In Loop) - Data Line | C4 |
DMM11 | I | Debug Interface (Hardware In Loop) - Data Line | A3 |
DMM12 | I | Debug Interface (Hardware In Loop) - Data Line | B4 |
DMM13 | I | Debug Interface (Hardware In Loop) - Data Line | A4 |
DMM14 | I | Debug Interface (Hardware In Loop) - Data Line | C5 |
DMM15 | I | Debug Interface (Hardware In Loop) - Data Line | B5 |
DMM_CLK | I | Debug Interface (Hardware In Loop) - Clock | U3 |
DMM_MUX_IN | I | Debug Interface (Hardware In Loop) Mux Select between DMM1 and DMM2 (Two Instances) | L3, M3, U12 |
DMM_SYNC | I | Debug Interface (Hardware In Loop) - Sync | U4 |
DSS_UART_TX | O | Debug UART Transmit [DSP] | D2, F2, G3, H2, L1 |
EPWM1A | O | PWM Module 1 - Output A | B4, U16, V13 |
EPWM1B | O | PWM Module 1 - Output B | A4, M2, U16, V10 |
EPWM1SYNCI | I | PWM Module 1 - Sync Input | C3, L3 |
EPWM1SYNCO | I | PWM Module 1 - Sync Output | B3 |
EPWM2A | O | PWM Module 2- Output A | C5, M2, U16, V10, V16 |
EPWM2B | O | PWM Module 2 - Output B | B5, V16 |
EPWM2SYNCO | O | PWM Module 2 - Sync Output | V3 |
EPWM3A | O | PWM Module 3 - Output A | C4, V16 |
EPWM3B | O | PWM Module 3 - Output A | A3 |
EPWM3SYNCO | O | PWM Module 3 - Sync Output | U5 |
GPIO_0 | IO | General-purpose I/O | M2 |
GPIO_1 | IO | General-purpose I/O | L3 |
GPIO_2 | IO | General-purpose I/O | K3 |
GPIO_3 | IO | General-purpose I/O | D2 |
GPIO_4 | IO | General-purpose I/O | D3 |
GPIO_5 | IO | General-purpose I/O | E2 |
GPIO_6 | IO | General-purpose I/O | J2 |
GPIO_7 | IO | General-purpose I/O | H2 |
GPIO_8 | IO | General-purpose I/O | H3 |
GPIO_9 | IO | General-purpose I/O | G2 |
GPIO_10 | IO | General-purpose I/O | J3 |
GPIO_11 | IO | General-purpose I/O | K2 |
GPIO_12 | IO | General-purpose I/O | B2 |
GPIO_13 | IO | General-purpose I/O | M2 |
GPIO_14 | IO | General-purpose I/O | U16 |
GPIO_15 | IO | General-purpose I/O | V16 |
GPIO_16 | IO | General-purpose I/O | L3 |
GPIO_17 | IO | General-purpose I/O | T3 |
GPIO_18 | IO | General-purpose I/O | U8 |
GPIO_19 | IO | General-purpose I/O | F2 |
GPIO_20 | IO | General-purpose I/O | D1 |
GPIO_21 | IO | General-purpose I/O | G1 |
GPIO_22 | IO | General-purpose I/O | G3 |
GPIO_23 | IO | General-purpose I/O | U9 |
GPIO_24 | IO | General-purpose I/O | U10 |
GPIO_25 | IO | General-purpose I/O | V13 |
GPIO_26 | IO | General-purpose I/O | K3 |
GPIO_27 | IO | General-purpose I/O | V10 |
GPIO_28 | IO | General-purpose I/O | U12 |
GPIO_29 | IO | General-purpose I/O | M3 |
GPIO_30 | IO | General-purpose I/O | C2, D2 |
GPIO_31 | IO | General-purpose I/O | U7 |
GPIO_32 | IO | General-purpose I/O | U6 |
GPIO_33 | IO | General-purpose I/O | V5 |
GPIO_34 | IO | General-purpose I/O | U5 |
GPIO_35 | IO | General-purpose I/O | V3 |
GPIO_36 | IO | General-purpose I/O | M1 |
GPIO_37 | IO | General-purpose I/O | L2 |
GPIO_38 | IO | General-purpose I/O | L1 |
GPIO_39 | IO | General-purpose I/O | C3 |
GPIO_40 | IO | General-purpose I/O | B3 |
GPIO_41 | IO | General-purpose I/O | C4 |
GPIO_42 | IO | General-purpose I/O | A3 |
GPIO_43 | IO | General-purpose I/O | B4 |
GPIO_44 | IO | General-purpose I/O | A4 |
GPIO_45 | IO | General-purpose I/O | C5 |
GPIO_46 | IO | General-purpose I/O | B5 |
GPIO_47 | IO | General-purpose I/O | U3 |
I2C_SCL | IO | I2C Clock | G3, V16 |
I2C_SDA | IO | I2C Data | G1, U16 |
LVDS_TXP[0] | O | Differential data Out – Lane 0 | N2 |
LVDS_TXM[0] | O | Differential data Out – Lane 0 | N1 |
LVDS_TXP[1] | O | Differential data Out – Lane 1 | P2 |
LVDS_TXM[1] | O | Differential data Out – Lane 1 | P1 |
LVDS_CLKP | O | Differential clock Out | R1 |
LVDS_CLKM | O | Differential clock Out | R2 |
LVDS_FRCLKP | O | Differential Frame Clock | T1 |
LVDS_FRCLKM | O | Differential Frame Clock | T2 |
MCU_CLKOUT | O | Programmable clock given out to external MCU or the processor | V13 |
MSS_UARTA_RX | I | Main Subsystem - UART A Receive | E2, U9, V16 |
MSS_UARTA_TX | O | Main Subsystem - UART A Transmit | D3, U7, U10, U16 |
MSS_UARTB_RX | IO | Main Subsystem - UART B Receive | U12, V16 |
MSS_UARTB_TX | O | Main Subsystem - UART B Transmit | D3, E2, K3, M1, T3, U10, U16 |
NDMM_EN | I | Debug Interface (Hardware In Loop) Enable - Active Low Signal | U10, U16 |
NERROR_IN | I | Failsafe input to the device. Nerror output from any other device can be concentrated in the error signaling monitor module inside the device and appropriate action can be taken by Firmware | U14 |
NERROR_OUT | O | Open drain fail safe output signal. Connected to PMIC/Processor/MCU to indicate that some severe criticality fault has happened. Recovery would be through reset. | U15 |
PMIC_CLKOUT | O | Output Clock from AWR6843AOP device for PMIC | K3, M2, V10 |
QSPI[0] | IO | QSPI Data Line #0 (Used with Serial Data Flash) | H3 |
QSPI[1] | I | QSPI Data Line #1 (Used with Serial Data Flash) | G2 |
QSPI[2] | I | QSPI Data Line #2 (Used with Serial Data Flash) | J3 |
QSPI[3] | I | QSPI Data Line #3 (Used with Serial Data Flash) | K2 |
QSPI_CLK | O | QSPI Clock (Used with Serial Data Flash) | H2 |
QSPI_CLK_EXT | I | QSPI Clock (Used with Serial Data Flash) | D3 |
QSPI_CS_N | O | QSPI Chip Select (Used with Serial Data Flash) | J2 |
RS232_RX | I | Debug UART (Operates as Bus Master) - Receive Signal | V16 |
RS232_TX | O | Debug UART (Operates as Bus Master) - Transmit Signal | U16 |
SOP[0] | I | Sense On Power - Line#0 | U10 |
SOP[1] | I | Sense On Power - Line#1 | M3 |
SOP[2] | I | Sense On Power - Line#2 | V10 |
SPIA_CLK | IO | SPI Channel A - Clock | D2 |
SPIA_CS_N | IO | SPI Channel A - Chip Select | C2 |
SPIA_MISO | IO | SPI Channel A - Master In Slave Out | D1 |
SPIA_MOSI | IO | SPI Channel A - Master Out Slave In | F2 |
SPIB_CLK | IO | SPI Channel B - Clock | E2, H2 |
SPIB_CS_N | IO | SPI Channel B Chip Select (Instance ID 0) | D3, J2 |
SPIB_CS_N_1 | IO | SPI Channel B Chip Select (Instance ID 1) | B2, L3, M3 |
SPIB_CS_N_2 | IO | SPI Channel B Chip Select (Instance ID 2) | G2, L3, M3 |
SPIB_MISO | IO | SPI Channel B - Master In Slave Out | G3, H3 |
SPIB_MOSI | IO | SPI Channel B - Master Out Slave In | G1, G2 |
SPI_HOST_INTR | O | Out of Band Interrupt to an external host communicating over SPI | B2 |
SYNC_IN | I | Low frequency Synchronization signal input | U12 |
SYNC_OUT | O | Low Frequency Synchronization Signal output | K3, L3, M3, U12 |
TCK | I | JTAG Test Clock | T3 |
TDI | I | JTAG Test Data Input | U9 |
TDO | O | JTAG Test Data Output | U10 |
TMS | I | JTAG Test Mode Signal | U8 |
TRACE_CLK | O | Debug Trace Output - Clock | U3 |
TRACE_CTL | O | Debug Trace Output - Control | U4 |
TRACE_DATA_0 | O | Debug Trace Output - Data Line | U7 |
TRACE_DATA_1 | O | Debug Trace Output - Data Line | U6 |
TRACE_DATA_2 | O | Debug Trace Output - Data Line | V5 |
TRACE_DATA_3 | O | Debug Trace Output - Data Line | U5 |
TRACE_DATA_4 | O | Debug Trace Output - Data Line | V3 |
TRACE_DATA_5 | O | Debug Trace Output - Data Line | M1 |
TRACE_DATA_6 | O | Debug Trace Output - Data Line | L2 |
TRACE_DATA_7 | O | Debug Trace Output - Data Line | L1 |
TRACE_DATA_8 | O | Debug Trace Output - Data Line | C3 |
TRACE_DATA_9 | O | Debug Trace Output - Data Line | B3 |
TRACE_DATA_10 | O | Debug Trace Output - Data Line | C4 |
TRACE_DATA_11 | O | Debug Trace Output - Data Line | A3 |
TRACE_DATA_12 | O | Debug Trace Output - Data Line | B4 |
TRACE_DATA_13 | O | Debug Trace Output - Data Line | A4 |
TRACE_DATA_14 | O | Debug Trace Output - Data Line | C5 |
TRACE_DATA_15 | O | Debug Trace Output - Data Line | B5 |
FRAME_START | O | Pulse signal indicating the start of each frame | K3, V10, V13 |
CHIRP_START | O | Pulse signal indicating the start of each chirp | K3, V10, V13 |
CHIRP_END | O | Pulse signal indicating the end of each chirp | K3, V10, V13 |
ADC_VALID | O | When high, indicating valid ADC samples | B2, L3, M2 |
WARM_RESET | IO | Open drain fail safe warm reset signal. Can be driven from PMIC for diagnostic or can be used as status signal that the device is going through reset. | U13 |
ANALOG | |||
NRESET | I | Power on reset for chip. Active low | U11 |
CLKP | I | In XTAL mode: Differential port for reference crystal In External clock mode: Single ended input reference clock port | A7 |
CLKM | I | In XTAL mode: Differential port for reference crystal In External clock mode: Connect this port to ground | B7 |
OSC_CLKOUT | O | Reference clock output from clocking sub system after cleanup PLL (1.4-V output voltage swing). | A14, K3 |
VBGAP | O | Device's Band Gap Reference Output | A16 |
VDDIN | Power | 1.2V digital power supply | E1, J1, V4, V8, V15 |
VIN_SRAM | Power | 1.2V power rail for internal SRAM | A5, V6, V12 |
VNWA | Power | 1.2V power rail for SRAM array back bias | C1, V7, V14 |
VIOIN | Power | I/O Supply (3.3V or 1.8V): All CMOS I/Os would operate on this supply | H1, V9 |
VIOIN_18 | Power | 1.8V supply for CMOS IO | B1, F1, K1, V11 |
VIN_18CLK | Power | 1.8V supply for clock module | C15, C18 |
VIOIN_18DIFF | Power | 1.8V supply for LVDS port | U2 |
VPP | Power | Voltage supply for fuse chain | V2 |
VIN_13RF1 | Power | 1.3V Analog and RF supply,VIN_13RF1 and VIN_13RF2 could be shorted on the board | J16, J17, J18 |
VIN_13RF2 | Power | 1.3V Analog and RF supply | H16, H17, H18 |
VIN_18BB | Power | 1.8V Analog base band power supply | M16, M17, M18 |
VIN_18VCO | Power | 1.8V RF VCO supply | A12, C11 |
VSS | Ground | Digital ground | A1, A2, E3, F3, N3, P3, R3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, U1, V1 |
VSSA | Ground | Analog ground | A6, A8, A11, A13, A15, A17, A18, B6, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18, C6, C7, C8, C12, C13, C14, C16, C17, D16, D17, D18, E16, E17, E18, F16, F17, F18, K16, K17, K18, L16, L17, L18, N16, N17, N18, P16, R16, R17, T17, U17, U18, V17, V18 |
VOUT_14APLL | O | Internal LDO output | A10 |
VOUT_14SYNTH | O | Internal LDO output | A9 |
VOUT_PA | IO | Internal LDO output | G16, G17, G18 |
Analog Test1 / GPADC1 | IO | Analog IO dedicated for ADC service | P18 |
Analog Test2 / GPADC2 | IO | Analog IO dedicated for ADC service | P17 |
Analog Test3 / GPADC3 | IO | Analog IO dedicated for ADC service | R18 |
Analog Test4 / GPADC4 | IO | Analog IO dedicated for ADC service | T18 |
ANAMUX / GPADC5 | IO | Analog IO dedicated for ADC service | C9 |
VSENSE / GPADC6 | IO | Analog IO dedicated for ADC service | C10 |