SWRS246C November 2020 – July 2022 AWR6843AOP
PRODUCTION DATA
PARAMETERS(1)(2) | MIN | MAX | UNIT | |
---|---|---|---|---|
VDDIN | 1.2 V digital power supply | –0.5 | 1.4 | V |
VIN_SRAM | 1.2 V power rail for internal SRAM | –0.5 | 1.4 | V |
VNWA | 1.2 V power rail for SRAM array back bias | –0.5 | 1.4 | V |
VIOIN | I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this supply. | –0.5 | 3.8 | V |
VIOIN_18 | 1.8 V supply for CMOS IO | –0.5 | 2 | V |
VIN_18CLK | 1.8 V supply for clock module | –0.5 | 2 | V |
VIOIN_18DIFF | 1.8 V supply for LVDS port | –0.5 | 2 | V |
VIN_13RF1 | 1.3 V Analog and RF supply, VIN_13RF1 and VIN_13RF2 could be shorted on the board. | –0.5 | 1.45 | V |
VIN_13RF2 | ||||
VIN_13RF1 (1-V Internal LDO bypass mode) |
Device supports mode where external Power Management block can supply 1 V on VIN_13RF1 and VIN_13RF2 rails. In this configuration, the internal LDO of the device would be kept bypassed. | –0.5 | 1.4 | V |
VIN_13RF2 (1-V Internal LDO bypass mode) |
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VIN_18BB | 1.8-V Analog baseband power supply | –0.5 | 2 | V |
VIN_18VCO supply | 1.8-V RF VCO supply | –0.5 | 2 | V |
Input and output voltage range | Dual-voltage LVCMOS inputs, 3.3 V or 1.8 V (Steady State) | –0.3V | VIOIN + 0.3 | V |
Dual-voltage LVCMOS inputs, operated at 3.3 V/1.8 V (Transient Overshoot/Undershoot) or external oscillator input | VIOIN + 20% up to 20% of signal period | |||
CLKP, CLKM | Input ports for reference crystal | –0.5 | 2 | V |
Clamp current | Input or Output Voltages 0.3 V above or below their respective power rails. Limit clamp current that flows through the internal diode protection cells of the I/O. | –20 | 20 | mA |
TJ | Operating junction temperature range | –40 | 125 | °C |
TSTG | Storage temperature range after soldered onto PC board | –55 | 150 | °C |