SWRS273C November   2021  – July 2024 AWR2944

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Device Comparison
    1. 4.1 Related Products
  6. 5 Pin Configurations and Functions
    1. 5.1 Pin Diagram
    2. 5.2 Pin Attributes
    3. 5.3 Signal Descriptions - Digital
    4. 5.4 Signal Descriptions - Analog
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Power-On Hours (POH)
    4. 6.4  Recommended Operating Conditions
    5. 6.5  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.5.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 6.5.2 Hardware Requirements
      3. 6.5.3 Impact to Your Hardware Warranty
    6. 6.6  Power Supply Specifications
    7. 6.7  Power Consumption Summary
    8. 6.8  RF Specifications
    9. 6.9  Thermal Resistance Characteristics
    10. 6.10 Power Supply Sequencing and Reset Timing
    11. 6.11 Input Clocks and Oscillators
      1. 6.11.1 Clock Specifications
    12. 6.12 Peripheral Information
      1. 6.12.1  QSPI Flash Memory Peripheral
        1. 6.12.1.1 QSPI Timing Conditions
        2. 6.12.1.2 QSPI Timing Requirements #GUID-CD30070D-F132-4A2C-92CD-5AA96AE70B94/GUID-97D19708-D87E-443B-9ADF-1760CFEF6F4C #GUID-CD30070D-F132-4A2C-92CD-5AA96AE70B94/GUID-0A61EEC9-2B95-4C27-B219-18D27C8F9430
        3. 6.12.1.3 QSPI Switching Characteristics #GUID-20B35D26-AFE6-451C-B9E9-B3F2FA08097C/T4362547-64 #GUID-20B35D26-AFE6-451C-B9E9-B3F2FA08097C/T4362547-65
      2. 6.12.2  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 6.12.2.1 MibSPI Peripheral Description
        2. 6.12.2.2 MibSPI Transmit and Receive RAM Organization
          1. 6.12.2.2.1 SPI Timing Conditions
          2. 6.12.2.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-20BA2ACF-4FC2-43F6-960F-1A4CA56E65A6/T4362547-236 #GUID-20BA2ACF-4FC2-43F6-960F-1A4CA56E65A6/T4362547-237 #GUID-20BA2ACF-4FC2-43F6-960F-1A4CA56E65A6/T4362547-238
          3. 6.12.2.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-517E5284-3345-461F-B07F-EB95741B1272/T4362547-244 #GUID-517E5284-3345-461F-B07F-EB95741B1272/T4362547-245 #GUID-517E5284-3345-461F-B07F-EB95741B1272/T4362547-246
        3. 6.12.2.3 SPI Peripheral Mode I/O Timings
          1. 6.12.2.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-5C88F9F6-787B-49E2-984F-02158AB0C326/T4362547-70 #GUID-5C88F9F6-787B-49E2-984F-02158AB0C326/T4362547-71 #GUID-5C88F9F6-787B-49E2-984F-02158AB0C326/T4362547-73
      3. 6.12.3  Ethernet Switch (RGMII/RMII/MII) Peripheral
        1. 6.12.3.1  RGMII/MII Timing Conditions
        2. 6.12.3.2  RGMII Transmit Clock Switching Characteristics
        3. 6.12.3.3  RGMII Transmit Data and Control Switching Characteristics
        4. 6.12.3.4  RGMII Receive Clock Timing Requirements
        5. 6.12.3.5  RGMII Receive Data and Control Timing Requirements
        6. 6.12.3.6  RMII Transmit Clock Switching Characteristics
        7. 6.12.3.7  RMII Transmit Data and Control Switching Characteristics
        8. 6.12.3.8  RMII Receive Clock Timing Requirements
        9. 6.12.3.9  RMII Receive Data and Control Timing Requirements
        10. 6.12.3.10 MII Transmit Switching Characteristics
        11. 6.12.3.11 MII Receive Clock Timing Requirements
        12. 6.12.3.12 MII Receive Timing Requirements
        13. 6.12.3.13 MII Transmit Clock Timing Requirements
        14. 6.12.3.14 MDIO Interface Timings
      4. 6.12.4  LVDS/Aurora Instrumentation and Measurement Peripheral
        1. 6.12.4.1 LVDS Interface Configuration
        2. 6.12.4.2 LVDS Interface Timings
      5. 6.12.5  UART Peripheral
        1. 6.12.5.1 SCI Timing Requirements
      6. 6.12.6  Inter-Integrated Circuit Interface (I2C)
        1. 6.12.6.1 I2C Timing Requirements #GUID-437677C7-D935-4733-A64D-553EFECA73F7/T4362547-185
      7. 6.12.7  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 6.12.7.1 Dynamic Characteristics for the CAN-FD TX and RX Pins
      8. 6.12.8  CSI2 Receiver Peripheral
        1. 6.12.8.1 CSI2 Switching Characteristics
      9. 6.12.9  Enhanced Pulse-Width Modulator (ePWM)
      10. 6.12.10 General-Purpose Input/Output
        1. 6.12.10.1 Switching Characteristics for Output Timing versus Load Capacitance (CL) #GUID-46919170-3C9C-440C-879B-A7700B77517D/T4362547-45 #GUID-46919170-3C9C-440C-879B-A7700B77517D/T4362547-50
    13. 6.13 Emulation and Debug
      1. 6.13.1 Emulation and Debug Description
      2. 6.13.2 JTAG Interface
        1. 6.13.2.1 Timing Requirements for IEEE 1149.1 JTAG
        2. 6.13.2.2 Switching Characteristics for IEEE 1149.1 JTAG
      3. 6.13.3 ETM Trace Interface
        1. 6.13.3.1 ETM TRACE Timing Requirements
        2. 6.13.3.2 ETM TRACE Switching Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Subsystems
      1. 7.3.1 RF and Analog Subsystem
        1. 7.3.1.1 RF Clock Subsystem
        2. 7.3.1.2 Transmit Subsystem
        3. 7.3.1.3 Receive Subsystem
      2. 7.3.2 Processor Subsystem
      3. 7.3.3 Automotive Interfaces
    4. 7.4 Other Subsystems
      1. 7.4.1 Hardware Accelerator Subsystem
      2. 7.4.2 Security – Hardware Security Module
      3. 7.4.3 ADC Channels (Service) for User Application
  9. 8 Monitoring and Diagnostics
    1. 8.1 Monitoring and Diagnostic Mechanisms
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Application Information
    2. 9.2 Short and Medium Range Radar
    3. 9.3 Reference Schematic
  11. 10Device and Documentation Support
    1. 10.1 Device Support
    2. 10.2 Device Nomenclature
    3. 10.3 Tools and Software
    4. 10.4 Documentation support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Receiving Notification of Documentation Updates
    8. 10.8 Electrostatic Discharge Caution
    9. 10.9 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

11 Revision History

Changes from May 10, 2024 to July 30, 2024 (from Revision B (May 2024) to Revision C (July 2024))

  • (Features) : Added AWR2944LC part to Features bulletsGo
  • (Global) : Updated HWA references from 2.0 to 2.1Go
  • (Description) : Added AWR2944ALBGALTQ1 to Device Information tableGo
  • (Description) : Added Device Variant column to Device Information tableGo
  • (Device Comparison) : Added AWR2944LC columnGo
  • (Signal Descriptions - Digital): Added LVDS and Aurora interfaces noteGo
  • (Overview) : Removed second paragraphGo
  • (Transmit Subsystem) : Updated transmit chain valueGo

Changes from March 31, 2023 to May 10, 2024 (from Revision A (March 2023) to Revision B (May 2024))

  • (Title): Updated '76- and 81-GHz' to '76 to 81GHz' Go
  • (Features) : Updated 5GHz available bandwidth to over 4GHz continuous bandwidthGo
  • (Functional Block Diagram): Updated the diagram to add ADC buffer sizeGo
  • (Pin Diagram): Added overline on all instances of SPI and QSPI chip selectGo
  • (Pin Attributes): Added overline on all instances of SPI and QSPI chip selectGo
  • (Signal Descriptions - Digital): Added overline on all instances of SPI and QSPI chip selectGo
  • (Absolute Maximum Ratings): Moved temp sensor accuracy to this section from RF SpecificationGo
  • (VPP specification) : New section added with VPP specificationsGo
  • (VPP specification) : Duration of VPP supply updated.Go
  • (RF Specifications): Updated 1dB compression point and ADC resolution valuesGo
  • (Power Supply Sequencing): Added overline on all instances of SPI and QSPI chip selectGo
  • (Ethernet Switch (RGMII/RMII/MII)):Removed instance of "TBD" Go
  • (Functional Block Diagram): Updated the diagram to add ADC buffer sizeGo
  • (Receive subsystem) : Configurable cut-off frequency is updated to 300kHz from 350kHz.Go