SWRS304A October   2024  – December 2024 CC2745P10-Q1 , CC2745R10-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagram—RHA package
    2. 6.2 Signal Descriptions—RHA Package
    3. 6.3 Connections for Unused Pins and Modules—RHA Package
    4. 6.4 RHA Peripheral Pin Mapping
    5. 6.5 RHA Peripheral Signal Descriptions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD and MSL Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  DC/DC
    5. 7.5  GLDO
    6. 7.6  Power Supply and Modules
    7. 7.7  Battery Monitor
    8. 7.8  BATMON Temperature Sensor
    9. 7.9  Power Consumption—Power Modes
    10. 7.10 Power Consumption—Radio Modes
    11. 7.11 Nonvolatile (Flash) Memory Characteristics
    12. 7.12 Thermal Resistance Characteristics
    13. 7.13 RF Frequency Bands
    14. 7.14 Bluetooth Low Energy—Receive (RX)
    15. 7.15 Bluetooth Low Energy—Transmit (TX)
    16. 7.16 Bluetooth Channel Sounding
    17. 7.17 2.4GHz RX/TX CW
    18. 7.18 Timing and Switching Characteristics
      1. 7.18.1 Reset Timing
      2. 7.18.2 Wakeup Timing
      3. 7.18.3 Clock Specifications
        1. 7.18.3.1 48 MHz Crystal Oscillator (HFXT)
        2. 7.18.3.2 96 MHz RC Oscillator (HFOSC)
        3. 7.18.3.3 80/90/98 MHz RC Oscillator (AFOSC)
        4. 7.18.3.4 32 kHz Crystal Oscillator (LFXT)
        5. 7.18.3.5 32 kHz RC Oscillator (LFOSC)
    19. 7.19 Peripheral Characteristics
      1. 7.19.1 UART
        1. 7.19.1.1 UART Characteristics
      2. 7.19.2 SPI
        1. 7.19.2.1 SPI Characteristics
        2. 7.19.2.2 SPI Controller Mode
        3. 7.19.2.3 SPI Timing Diagrams - Controller Mode
        4. 7.19.2.4 SPI Peripheral Mode
        5. 7.19.2.5 SPI Timing Diagrams - Peripheral Mode
      3. 7.19.3 I2C
        1. 7.19.3.1 I2C Characteristics
        2. 7.19.3.2 I2C Timing Diagram
      4. 7.19.4 I2S
        1. 7.19.4.1 I2S Controller Mode
        2. 7.19.4.2 I2S Peripheral Mode
      5. 7.19.5 CAN-FD
        1. 7.19.5.1 CAN-FD Characteristics
      6. 7.19.6 GPIO
        1. 7.19.6.1 GPIO DC Characteristics
      7. 7.19.7 ADC
        1. 7.19.7.1 Analog-to-Digital Converter (ADC) Characteristics
      8. 7.19.8 Comparators
        1. 7.19.8.1 Low Power Comparator
      9. 7.19.9 Voltage Glitch Monitor
    20. 7.20 Typical Characteristics
      1. 7.20.1 MCU Current
      2. 7.20.2 RX Current
      3. 7.20.3 TX Current
      4. 7.20.4 RX Performance
      5. 7.20.5 TX Performance
      6. 7.20.6 ADC Performance
  9. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  System CPU
    3. 8.3  Radio (RF Core)
      1. 8.3.1 Bluetooth Low Energy
    4. 8.4  Memory
    5. 8.5  Hardware Security Module (HSM)
    6. 8.6  Cryptography
    7. 8.7  Timers
    8. 8.8  Algorithm Processing Unit (APU)
    9. 8.9  Serial Peripherals and I/O
    10. 8.10 Battery and Temperature Monitor
    11. 8.11 Voltage Glitch Monitor (VGM)
    12. 8.12 µDMA
    13. 8.13 Debug
    14. 8.14 Power Management
    15. 8.15 Clock Systems
    16. 8.16 Network Processor
    17. 8.17 Integrated BALUN, High Power PA (Power Amplifier)
  10. 9 Application, Implementation, and Layout
    1. 9.1 Reference Designs
    2. 9.2 Junction Temperature Calculation
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
      1. 10.2.1 SimpleLink™ Microcontroller Platform
      2. 10.2.2 Software License and Notice
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.8 Algorithm Processing Unit (APU)

The APU is a generic mathematical acceleration module that operates with single-precision floating point numbers (IEEE 754 format) and is optimized to work with complex numbers. The APU runs at 96MHz, operates autonomously from the main CPU in the system, and can be used to offload numerically intensive operations. This module handles efficient vector (and matrix) operations and sustains one complex Multiply-and-Add operation per clock cycle. These operations are extensively used in advanced post-processing algorithms needed for accurate phase-based distance estimation using the Bluetooth® LE Channel Sounding mechanism; thereby, optimizing the overall channel sounding-based distance estimation latency and energy efficiency.

The APU has 8KB of local data memory (separate from the system RAM) where the application can read/write data. The APU incorporates a programmable core to handle advanced APIs developed for the APU hardware accelerator submodules. The SimpleLink™ Low Power F3 software development kit (SDK) includes the APU APIs that are executed by the APU programmable core within RAM-based local program memory (separate from the system RAM and VCE data RAM).

The user application handles chain-calling the different APU APIs and moving data in/out of the APU local data memory. The SimpleLink Low Power F3 software development kit (SDK) supports SW drivers and examples to enable APU operations.