SWRS304A October   2024  – December 2024 CC2745P10-Q1 , CC2745R10-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Functional Block Diagram
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagram—RHA package
    2. 6.2 Signal Descriptions—RHA Package
    3. 6.3 Connections for Unused Pins and Modules—RHA Package
    4. 6.4 RHA Peripheral Pin Mapping
    5. 6.5 RHA Peripheral Signal Descriptions
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD and MSL Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  DC/DC
    5. 7.5  GLDO
    6. 7.6  Power Supply and Modules
    7. 7.7  Battery Monitor
    8. 7.8  BATMON Temperature Sensor
    9. 7.9  Power Consumption—Power Modes
    10. 7.10 Power Consumption—Radio Modes
    11. 7.11 Nonvolatile (Flash) Memory Characteristics
    12. 7.12 Thermal Resistance Characteristics
    13. 7.13 RF Frequency Bands
    14. 7.14 Bluetooth Low Energy—Receive (RX)
    15. 7.15 Bluetooth Low Energy—Transmit (TX)
    16. 7.16 Bluetooth Channel Sounding
    17. 7.17 2.4GHz RX/TX CW
    18. 7.18 Timing and Switching Characteristics
      1. 7.18.1 Reset Timing
      2. 7.18.2 Wakeup Timing
      3. 7.18.3 Clock Specifications
        1. 7.18.3.1 48 MHz Crystal Oscillator (HFXT)
        2. 7.18.3.2 96 MHz RC Oscillator (HFOSC)
        3. 7.18.3.3 80/90/98 MHz RC Oscillator (AFOSC)
        4. 7.18.3.4 32 kHz Crystal Oscillator (LFXT)
        5. 7.18.3.5 32 kHz RC Oscillator (LFOSC)
    19. 7.19 Peripheral Characteristics
      1. 7.19.1 UART
        1. 7.19.1.1 UART Characteristics
      2. 7.19.2 SPI
        1. 7.19.2.1 SPI Characteristics
        2. 7.19.2.2 SPI Controller Mode
        3. 7.19.2.3 SPI Timing Diagrams - Controller Mode
        4. 7.19.2.4 SPI Peripheral Mode
        5. 7.19.2.5 SPI Timing Diagrams - Peripheral Mode
      3. 7.19.3 I2C
        1. 7.19.3.1 I2C Characteristics
        2. 7.19.3.2 I2C Timing Diagram
      4. 7.19.4 I2S
        1. 7.19.4.1 I2S Controller Mode
        2. 7.19.4.2 I2S Peripheral Mode
      5. 7.19.5 CAN-FD
        1. 7.19.5.1 CAN-FD Characteristics
      6. 7.19.6 GPIO
        1. 7.19.6.1 GPIO DC Characteristics
      7. 7.19.7 ADC
        1. 7.19.7.1 Analog-to-Digital Converter (ADC) Characteristics
      8. 7.19.8 Comparators
        1. 7.19.8.1 Low Power Comparator
      9. 7.19.9 Voltage Glitch Monitor
    20. 7.20 Typical Characteristics
      1. 7.20.1 MCU Current
      2. 7.20.2 RX Current
      3. 7.20.3 TX Current
      4. 7.20.4 RX Performance
      5. 7.20.5 TX Performance
      6. 7.20.6 ADC Performance
  9. 8 Detailed Description
    1. 8.1  Overview
    2. 8.2  System CPU
    3. 8.3  Radio (RF Core)
      1. 8.3.1 Bluetooth Low Energy
    4. 8.4  Memory
    5. 8.5  Hardware Security Module (HSM)
    6. 8.6  Cryptography
    7. 8.7  Timers
    8. 8.8  Algorithm Processing Unit (APU)
    9. 8.9  Serial Peripherals and I/O
    10. 8.10 Battery and Temperature Monitor
    11. 8.11 Voltage Glitch Monitor (VGM)
    12. 8.12 µDMA
    13. 8.13 Debug
    14. 8.14 Power Management
    15. 8.15 Clock Systems
    16. 8.16 Network Processor
    17. 8.17 Integrated BALUN, High Power PA (Power Amplifier)
  10. 9 Application, Implementation, and Layout
    1. 9.1 Reference Designs
    2. 9.2 Junction Temperature Calculation
  11. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
    2. 10.2 Tools and Software
      1. 10.2.1 SimpleLink™ Microcontroller Platform
      2. 10.2.2 Software License and Notice
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.14 Power Management

To minimize power consumption, the CC27xx devices support multiple power modes and power management features (see Table 8-2).

Table 8-2 Power Modes
MODESOFTWARE CONFIGURABLE POWER MODES (1)RESET PIN HELD
ACTIVEIDLESTANDBYSHUTDOWN
CPUActiveOffOffOffOff
FlashOnAvailableOffOffOff
SRAMOnOnRetentionOffOff
RadioAvailableAvailableOffOffOff
Supply SystemOnOnDuty CycledOffOff
CPU register retentionFullFullFull (2)NoNo
SRAM retentionFullFullFullOffOff
96 MHz high-speed clock (HFCLK)HFOSC (3)HFOSC (3)Duty Cycled (4)OffOff

80/90/98 MHz Auxiliary Frequency Oscillator (AFOSC)

AFOSCAFOSC

Off

(5)		OffOff
32 kHz low-speed clock (LFCLK)LFXT or LFOSCLFXT or LFOSCLFXT or LFOSCOffOff
PeripheralsAvailableAvailableIOC, BATMON, RTC, LPCOMPOffOff
Wake-up on RTCN/AAvailableAvailableOffOff
Wake-up on pin edgeN/AAvailableAvailableAvailableOff
Wake-up on reset pinOnOnOnOnOn
Brownout detector (BOD)OnOnDuty CycledOffOff
Power-on reset (POR)OnOnOnOnOn
Watchdog timer (WDT)AvailableAvailableAvailableOffOff
(1) “Available” indicates that the specific IP or feature can be enabled by the user application in the corresponding device operating modes. “On” indicates that the specific IP or feature is turned on irrespective of the user application configuration of the device in the corresponding device operating mode. “Off” indicates that the specific IP or feature is turned off and not available for the user application in the corresponding device operating mode.
(2) Software-based retention of CPU registers with context save and restore when entering and exiting standby power mode.
(3) In active and idle power modes, the HFOSC tracking loop is enabled by default, thereby enabling 48MHz HFXT as well.
(4) If LFOSC HW calibration is enabled in standby mode, then, HFOSC tracking loop requiring HFXT is dutycycled. If not, only HFOSC is duty-cycled during recharge cycles.
(5) AFOSC standby behavior is controlled by AFOSCCTL.AUTODIS. When set, AFOSC is disabled when entering standby. Enabling AFOSC again on standby exit must be done by software.

In the Active mode, both of MCU and AON power domains are powered. Clock gating is used to minimize power consumption. Clock gating to peripherals/subsystems is controlled manually by the CPU.

In Idle mode, the CPU is in sleep but selected peripherals and subsystems (such as the radio) can be active. Infrastructure (Flash, ROM, SRAM, bus) clock gating is possible depending on the state of the DMA and debug subsystem.

In Standby mode, only the always-on (AON) domain is active. An external wake-up event, RTC event, or comparator event (LP-COMP) is required to bring the device back to active mode. Pin Reset will also drive the device from Standby to Active. MCU peripherals with retention do not need to be reconfigured when waking up again, and the CPU continues execution from where it went into standby mode. All GPIOs are latched in standby mode.

In Shutdown mode, the device is entirely turned off (including the AON domain), and the I/Os are latched with the value they had before entering shutdown mode. A change of state on any I/O pin defined as a wake from shutdown pin wakes up the device and functions as a reset trigger. The CPU can differentiate between reset in this way and reset-by-reset pin or power-on reset, or thermal shutdown reset, by reading the reset status register. The only states retained in this mode are the latched I/O state, the 3V register bank, and the flash memory contents.

Note: The power, RF, and clock management for the CC27xx devices require specific configuration and handling by software for optimized performance. This configuration and handling are implemented in the TI-provided drivers that are part of the SimpleLink Low Power F3 software development kit (SDK). Therefore, TI highly recommends using this software framework for all application development on the device. The complete SDK with FreeRTOS, device drivers, and examples are offered free of charge in source code.