SWRS304A October 2024 – December 2024 CC2745P10-Q1 , CC2745R10-Q1
PRODUCTION DATA
A large selection of timers are available as part of the CC27xx devices. These timers are:
The RTC is a 67-bit, 2-channel timer running on the LFCLK system clock. The RTC is active in STANDBY and ACTIVE power states. Upon asynchronous device resets (that is, reset pin, exit from shutdown, LF clock loss, and so on), the RTC is reset. However, upon internally generated synchronous device resets (for example, WDT, debug reset, system reset request, and so on), the RTC is not reset.
The RTC accumulates time elapsed since its last reset on each LFCLK. It is also possible to update the RTC value as part of the RTC configuration to match a different time base. The RTC counter is incremented by LFCLK at a rate between 30kHz and 34kHz depending on the LF clock source. LFINC indicates the period of LFCLK in μs with an additional granularity of 16 fractional bits and is used to increment time in the RTC. Hardware measurement circuitry can automatically measure the LFCLK period whenever HFXT is running and update LFINC.
The counter can be read from two 32-bit registers. RTC.TIME8U has a range of approximately 9.5 hours with an LSB representing 8 microseconds. RTC.TIME524M has a range of approximately 71.4 years with an LSB representing 524 milliseconds.
There is hardware synchronization between the system timer (SYSTIM) and the RTC so that the multichannel and higher resolution SYSTIM remain in synchronization with the RTC’s time base.
The RTC has two channels: one compare channel and one capture channel which is capable of waking the device out of the standby power state. The RTC compare channel is typically used only by system software and only during the standby power state.
The SYSTIM is a 34-bit, 6-channel wrap-around timer with a per-channel selectable 32b time slice with either a 1μs resolution and 1h11m35s range or 250ns resolution and 17m54s range. One channel is reserved for system software, three channels are reserved for radio software and two channels are freely available to user applications. All user-available channels support both capture and single-shot compare (posting an event) operation.
For software convenience, a hardware synchronization mechanism automatically ensures that the RTC and SYSTIM share a common time base. Another software convenience feature is that SYSTIM qualifies any submitted compare values so that the timer channel will immediately trigger if the submitted event is in the immediate past (4.294s with 1μs resolution and 1.049s with 250ns resolution).
The CC27xx devices provide four LGPTs with 3 × 16-bit timers and 1× 32-bit timers, all running on up to 48MHz. The LGPTs support a wide range of features such as:
The timer capture/compare and PWM signals are connected to IOs through the IO controller module (IOC) and the internal timer event connections to CPU, DMA, and other peripherals are through the event fabric, which allows the timers to interact with signals such as GPIO inputs, other timers, DMA and ADC. Two LGPTs support quadrature decoder mode to enable buffered decoding of quadrature-encoded sensor signals. The LGPTs are available in device Active and Idle power modes.
CC27xx GP TIMER FEATURE | TIMER 0 | TIMER 1 | TIMER 2 | TIMER 3 |
---|---|---|---|---|
Counter Width | 16-bit | 16-bit | 16-bit | 32-bit |
Quadrature Decoder | Yes | No | Yes | No |
Park Mode on Fault | No | Yes | No | No |
Programmable Deadband Insertion | No | Yes | No | No |
The watchdog timer is used to regain control if the system operates incorrectly due to software errors. Upon counter expiry, the watchdog timer resets the device when periodic monitoring of the system components and tasks fails to verify proper functionality. The watchdog timer runs on a 32kHz clock rate and operates in device active, idle, and standby modes, and cannot be stopped once enabled.