SWRU553A September   2019  – February 2020 AWR1243 , AWR2243

 

  1.   AWRx Cascaded Radar RF Evaluation Module (MMWCAS-RF-EVM)
    1.     Trademarks
    2. 1 Getting Started
      1. 1.1 Introduction
      2. 1.2 EVM Revisions
      3. 1.3 Key Features
      4. 1.4 What is Included
        1. 1.4.1 Kit Hardware Contents
        2. 1.4.2 mmWave Studio and Matlab Post Processing
    3. 2 Hardware Description
      1. 2.1 Block Diagram
      2. 2.2 Attaching the MMWAVCAS-RF-EVM to the MMWAVCAS-DSP-EVM
      3. 2.3 Power Status LED Indicators
      4. 2.4 Reset LED Indicators
      5. 2.5 Connectors
        1. 2.5.1 Host Board Connectors(J4, J5)
        2. 2.5.2 Bench Power Connector(J6)
        3. 2.5.3 20 GHz LO Debug Connector (J3)
        4. 2.5.4 AWR OSC_CLKOUT Debug Header (J2)
        5. 2.5.5 AWR Debug Headers (J1_1, J1_2, J1_3, J1_4)
      6. 2.6 Antennas
        1. 2.6.1 TX and RX Antenna Arrays
        2. 2.6.2 PCB Antenna Element
          1. 2.6.2.1 RX Antenna Element Performance
          2. 2.6.2.2 TX Antenna Element Performance
        3. 2.6.3 Virtual Antenna Array
    4. 3 Design Files and Software Tools
      1. 3.1 Hardware Collateral
      2. 3.2 Software, Development Tools, and Example Codes for MMWCAS-RF-EVM
      3. 3.3 Critical AWRx Setup Notes
        1. 3.3.1 LDO Bypass Requirement
    5. 4 PCB Dimensions and Mounting Information
    6. 5 PCB Storage and Handling Recommendations
    7. 6 References
    8. 7 Regulatory Information
  2.   Revision History

2.1 Block Diagram

The MMWAVCAS-RF-EVM consists of four AWR mmWave SoC and their associated power, clocking, synchronization, LO and RF TX and RX circuits. Each AWRx RF TX and RX port is routed to an etched, series-fed, patch antenna element. Each AWRx on the RF board has a 4-port CSI2.0 transmitter which is used for sending radar IQ ADC data samples to an attached host processor CSI2.0 receiver set. All of the AWRx configuration, control and reset lines are made available on two host interface connectors (J4 and J5) implemented with Hirose FX23-120 connectors.

swru553-cascade-rf-design-spec-diagrams-system-block-diagram.gifFigure 4. MMWAVCAS-RF-EVM System Block Diagram

The AWR devices are separated into Master and Slave classes of devices. AWRx #1, the Master device, utilizes the AWRx architecture built in VCO, LO distribution, clock distribution and frame synchronization distribution to provide 40 MHz clock, 20 GHz LO and frame synchronization to the other three Slave devices – AWRx #2, AWRx #3 and AWRx #4. This allows the system to generate and receive synchronous FMCW chirps across the four device AWRx array of transmitters and receivers.

The LO distribution follows the star-network configuration described in AWR2243 Cascade. The master AWRx feeds a network of two Wilkinson power dividers, which in turn provide synchronous LO for the Master and Slave PA and mixer subsystems. All clock distribution, synchronization distribution and LO distribution requirements are documented in this referenced application note.

The Cascade RF board accepts 5V DC, 8A (max) power primarily through the host board connectors J4 and J5. A separate 6-pin power connector (J6) is available as an alternate power path. The primary 5V system rail provided by the host board is converted into the variousAWRx device rails by the LP87524P quad-channel, monolithic, buck-converter.