SWRU612 December   2023 CC3300 , CC3301 , CC3301MOD , CC3351

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Overview
  5. 2Schematic Considerations
    1. 2.1 Schematic Reference Design
    2. 2.2 Power Supply
      1. 2.2.1 Power Input/Output Requirements
      2. 2.2.2 Power-Up Sequence
        1. 2.2.2.1 SOP Modes
    3. 2.3 Clock Source
      1. 2.3.1 Fast Clock
      2. 2.3.2 Slow Clock
        1. 2.3.2.1 Slow Clock Generated Internally
        2. 2.3.2.2 Slow Clock Using an External Oscillator
    4. 2.4 Radio Frequency (RF)
    5. 2.5 Digital Interfaces
      1. 2.5.1 Reset
      2. 2.5.2 Secure Digital Input Output (SDIO)
        1. 2.5.2.1 SDIO Timing Diagram - Default Speed
        2. 2.5.2.2 SDIO Timing Diagram - High Speed
      3. 2.5.3 Serial Peripheral Interface (SPI)
        1. 2.5.3.1 SPI Timing Diagram
      4. 2.5.4 Universal Asynchronous Receiver-Transmitter (UART)
      5. 2.5.5 Serial Wire Debug (SWD)
      6. 2.5.6 Coexistence
  6. 3Layout Considerations
    1. 3.1 Layout Reference Design
      1. 3.1.1 Reference Design Layout
      2. 3.1.2 BP-CC3301 Design Layout
      3. 3.1.3 M2-CC3301 Design Layout
    2. 3.2 IC Thermal Pad
    3. 3.3 Radio Frequency (RF)
    4. 3.4 XTAL
    5. 3.5 Power Supplies
    6. 3.6 SDIO

3.6 SDIO

SDIO is the main communication interface with the host processor for WLAN functions, and can also be used for BLE functions in shared SDIO protocols. These signals are especially sensitive because of the clock, and should be designed as such.

The SDIO lines include SDIO_CLK, SDIO_CMD, SDIO_D0, SDIO_D1, SDIO_D2, and SDIO_D3. The SDIO_CLK signal in particular is very sensitive and should be regarded as such. In order to ensure reliable SDIO communication, the following layout considerations should be taken into account:

  • It is recommended that the SDIO lines have at least 5mils of width.
  • The SDIO traces should be as far away as possible from the other digital or analog signal traces.
  • It is recommended to add ground shielding around the SDIO bus.
  • The SDIO_CLK must be isolated from all other signals with ground vias (stitching vias) and adjacent ground planes. The signal trace should have a clearance of at least twice the trace width of the other SDIO signals.
  • Route the SDIO lines in parallel to each other with lengths as short as possible (to decrease propagation delay), and have a clearance of 1.5x the trace width.
  • The lengths of the SDIO traces must be length matched within 20 mil tolerance to provide the sampled data at the same time on all of the traces. For a visual example of length tuning, see Figure 3-15.

Figure 3-15 is sampled from the BP-CC3301 design files.

GUID-20231127-SS0I-CXS0-KGN8-B07QPJ1MLWV1-low.png Figure 3-15 Reference Layout for SDIO Signals