SWRU612 December   2023 CC3300 , CC3301 , CC3351

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Overview
  5. 2Schematic Considerations
    1. 2.1 Schematic Reference Design
    2. 2.2 Power Supply
      1. 2.2.1 Power Input/Output Requirements
      2. 2.2.2 Power-Up Sequence
        1. 2.2.2.1 SOP Modes
    3. 2.3 Clock Source
      1. 2.3.1 Fast Clock
      2. 2.3.2 Slow Clock
        1. 2.3.2.1 Slow Clock Generated Internally
        2. 2.3.2.2 Slow Clock Using an External Oscillator
    4. 2.4 Radio Frequency (RF)
    5. 2.5 Digital Interfaces
      1. 2.5.1 Reset
      2. 2.5.2 Secure Digital Input Output (SDIO)
        1. 2.5.2.1 SDIO Timing Diagram - Default Speed
        2. 2.5.2.2 SDIO Timing Diagram - High Speed
      3. 2.5.3 Serial Peripheral Interface (SPI)
        1. 2.5.3.1 SPI Timing Diagram
      4. 2.5.4 Universal Asynchronous Receiver-Transmitter (UART)
      5. 2.5.5 Serial Wire Debug (SWD)
      6. 2.5.6 Coexistence
  6. 3Layout Considerations
    1. 3.1 Layout Reference Design
      1. 3.1.1 Reference Design Layout
      2. 3.1.2 BP-CC3301 Design Layout
      3. 3.1.3 M2-CC3301 Design Layout
    2. 3.2 IC Thermal Pad
    3. 3.3 Radio Frequency (RF)
    4. 3.4 XTAL
    5. 3.5 Power Supplies
    6. 3.6 SDIO

2.4 Radio Frequency (RF)

For the CC330x family of devices, it is required to route out RF_BG (pin 2) for any radio frequency (RF) functionality. A band pass filter (BPF) is required along this path before reaching any radiative or conductive component. For the recommended BPF, see Table 2-1. It is also recommended to implement an impedance matching network (such as a 'PI' or 'L' network) for optimal RF performance. Table 2-2 is an example of schematic design for the RF path. Any deviation from these recommendations can cause performance to diverge from the data sheet specifications.

If implementing a RF switch (for utilizing antenna diversity), ensure that the RF_BG (pin 2) signal is routed through the band pass filter before the switch. The output of the band pass filter should be routed to the common port of the switch. ANT_SEL (pin 15) may be routed and used as the switching signal.

GUID-20231207-SS0I-V8JT-M09R-DMDGKMVQM3MN-low.svg Figure 2-2 Reference Schematic for RF Section