SWRU612 December   2023 CC3300 , CC3301 , CC3351

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Overview
  5. 2Schematic Considerations
    1. 2.1 Schematic Reference Design
    2. 2.2 Power Supply
      1. 2.2.1 Power Input/Output Requirements
      2. 2.2.2 Power-Up Sequence
        1. 2.2.2.1 SOP Modes
    3. 2.3 Clock Source
      1. 2.3.1 Fast Clock
      2. 2.3.2 Slow Clock
        1. 2.3.2.1 Slow Clock Generated Internally
        2. 2.3.2.2 Slow Clock Using an External Oscillator
    4. 2.4 Radio Frequency (RF)
    5. 2.5 Digital Interfaces
      1. 2.5.1 Reset
      2. 2.5.2 Secure Digital Input Output (SDIO)
        1. 2.5.2.1 SDIO Timing Diagram - Default Speed
        2. 2.5.2.2 SDIO Timing Diagram - High Speed
      3. 2.5.3 Serial Peripheral Interface (SPI)
        1. 2.5.3.1 SPI Timing Diagram
      4. 2.5.4 Universal Asynchronous Receiver-Transmitter (UART)
      5. 2.5.5 Serial Wire Debug (SWD)
      6. 2.5.6 Coexistence
  6. 3Layout Considerations
    1. 3.1 Layout Reference Design
      1. 3.1.1 Reference Design Layout
      2. 3.1.2 BP-CC3301 Design Layout
      3. 3.1.3 M2-CC3301 Design Layout
    2. 3.2 IC Thermal Pad
    3. 3.3 Radio Frequency (RF)
    4. 3.4 XTAL
    5. 3.5 Power Supplies
    6. 3.6 SDIO

3.4 XTAL

Figure 3-11 shows the placement and layout around the 40 MHz XTAL and its connections to the CC33xx IC.

Figure 3-11 is sampled from the BP-CC3301 design files.

GUID-20231121-SS0I-MHGK-XNQD-GGJTW22V09XB-low.png Figure 3-11 40MHz XTAL From BP-CC3301

When integrating the XTAL, please follow these guidelines:

  • The traces connecting the XTAL to the CC3301 (XTAL_P and XTAL_M) be as short as possible with matching trace length.
  • Place a 150 Ω resistor on the XTAL_P pin as close as possible to the CC33xx.
  • The two loading capacitors should be parallel to the edge of the XTAL.
  • On layer below the crystal (layer 2), place a cutout underneath the area of the XTAL and the loading capacitors. Check on the layer below that (layer 3) has good ground underneath the same area. For a visual representation, see Figure 3-12.
  • Wherever possible, there should be increased ground via stitching around the XTAL for optimal isolation.

Figure 3-12 is sampled from layer 3 of the M2-CC3301 design files.

GUID-20231205-SS0I-LKPK-ZMXH-WHTHJGDR9HWH-low.png Figure 3-12 Reference Layout for Layer Under XTAL Cutout