SWRU620 April   2024

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 Block Diagram
      2. 1.3.2 EVM Mux Block Diagram
    4. 1.4 Device Information
    5. 1.5 xWRL6432AOPEVM Antenna
  7. 2Hardware
    1. 2.1 PCB Material
    2. 2.2 Switches and LEDs
      1. 2.2.1 SOP Configuration
      2. 2.2.2 Switches
    3. 2.3 DC Jack
    4. 2.4 DCA1000 HD Connector
    5. 2.5 CANFD Connector
    6. 2.6 LIN PHY Connection
    7. 2.7 I2C Connections
      1. 2.7.1 EEPROM
      2. 2.7.2 On-Board Sensors
    8. 2.8 XDS110 Interface
    9. 2.9 FTDI Interface
  8. 3Software
    1. 3.1 Software Description
    2. 3.2 Flashing the Board
    3. 3.3 mmWave Out of Box Demo
      1. 3.3.1 XWRL6432AOP Demo Visualization Getting Started
    4. 3.4 DCA1000EVM Mode
  9. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layouts
      1. 4.2.1 PCB Storage and Handling Recommendations:
        1. 4.2.1.1 PCB Storage and Handling Recommendations:
        2. 4.2.1.2 Higher Power Demanding Applications
    3. 4.3 Bill of Materials (BOM)
  10. 5Additional Information
    1. 5.1 Trademarks
  11. 6Related Documentation
  12. 7TI E2E Community
  13. 8References

1.4 Device Information

The xWRL6432AOP mmWave Sensor device is an Antenna-on-Package (AOP) device that is an evolution within integrated single chip mmWave sensor based on FMCW radar technology. The device is capable of operation in the 57GHz to 64GHz band and is partitioned into mainly four power domains:

  • RF/Analog Sub-System: This block includes all the RF and Analog components required to transmit and receive the RF signals.
  • Front-End Controller sub-System (FECSS): FECSS contains ARM Cortex M3 processor, responsible for radar front-end configuration, control, and calibration.
  • Application Sub-System (APPSS): APPSS is where the device implements a user programmable ARM Cortex M4 allowing for custom control and automotive interface applications. Top Sub-System (TOPSS) is part of the APPSS power domain and contains the clocking and power management sub-blocks.
  • Hardware Accelerator (HWA): HWA block supplements the APPSS by offloading common radar processing such as FFT, Constant False Alarm rate (CFAR), scaling, and compression.

xWRL6432AOP is specifically designed to have separate knobs for each of the above-mentioned power domains to control the states (power ON or OFF) based on use case requirements. The device also features the capability to exercise various low-power states like sleep and deep sleep, where low-power sleep mode is achieved by clock gating and by turning off some of the internal IP blocks of the device. The device also provides the option of keeping some contents of the device, like application image or RF profile retained in such scenarios.

Additionally, the device is built with TI’s low power 45-nm RF CMOS process and enables unprecedented levels of integration in an extremely small form factor. xWRL6432AOP is designed for low power, self-monitored, ultra-accurate radar systems in the industrial applications.