SWRU622A August 2024 – September 2024 AWRL1432 , AWRL6432 , IWRL1432 , IWRL6432 , IWRL6432AOP
The reset registers can be used to identify if the type of reset that was triggered matches the intended reset the user wanted to trigger. Please see the tables below for descriptions of these registers and what the values in those register represent.
wWRLx432:TOP_PRCM:SYS_RST_CAUSE | Filed Name | Description | ||
---|---|---|---|---|
Bit#16 | SYS_RST_CAUSE_SYS_RST_CAUSE_CLR |
Clear's the sys_rst_cause register 0x0 -> sys_rst_cause capture enable 0x1 -> sys_rst_cause reg clear and disable |
||
Bit#<2:0> | SYS_RST_CAUSE_SYS_RST_CAUSE |
System Reset Cause register 3'b001 - POR reset 3'b010 - Warm reset due to soft register 3'b100 - Warm reset due to wdog |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-21 | RESERVED | R/W | X | |
20 | radar_state_is_deep_sleep | R | 0h | RADAR power FSM is in DEEP_SLEEP state |
19 | radar_state_is_go_to_deep_sleep | R | 0h | RADAR power FSM is in GO_TO_DEEP_SLEEP state |
18 | radar_state_is_sleep | R | 0h | RADAR power FSM is in SLEEP state |
17 | radar_state_is_idle | R | 0h | RADAR power FSM is in IDLE state |
16 | radar_state_is_wake_up | R | 0h | RADAR power FSM is in WAKEUP state |
15-9 | RESERVED | R/W | X | |
8 | wakeup_status_clear | R/W | 0h | Clear's the wakeup status and source register 0x 0 -> Wakeup status and source capture enable 0x 1 -> Wakeup status and source reg clear and disable |
7-2 | wakeup_source | R | 0h | It indicate wakeup source from SLEEP/DEEP SLEEP state
Bit 0 -> Sleep counter as Wakeup source Bit 1 -> UART as Wakeup source Bit 2 -> SPI as Wakeup source Bit 3 -> GPIO as Wakeup source Bit 4 -> RTC counter as Wakeup source Bit 5 -> FRC frame start intr as Wakeup source |
1-0 | wakeup_status | R | 0h | It indicates the wakeup status of the device, whether
it is Wakeup due to POR or from SLEEP/DEEP SLEEP state 0x 1 -> Wakeup from SLEEP 0x 2 -> Wakeup from DEEP SLEEP |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | X | |
7-0 | COMMON | R | 3h | Reset cause register for APP CPU 0x00 - All cleared 0x01 - Power On Reset (PoR) 0x02 - Subsystem Reset (Combination of Warm Reset initiated from PRCM using xWRLx432:TOP_PRCM:RST_APP_PD_SOFT_RESET and PoR reset) 0x04 - STC RESET 0x08 - Reserved 0x10 - CPU Only Reset triggered by writing to xWRLx432:APP_RCM:RST_FSM_TRIG<RST_FSM_TRIG_CPU> 0x20 - Core Reset initiated from PRCM using xWRLx432:TOP_PRCM:RST_SOFT_APP_CORE_SYSRESET_REQ (reset CPU unconditionally - by debugger) or xWRLx432:TOP_PRCM:APP_CORE_SYSRESET_PARAM_WAKEUP_OUT_STATE 0x40 - Reserved |
Bit | Source |
---|---|
[3:0] | Reset Reason
Identification by bootloader M_BOOT_RESET_REASON_PORZ:
(0x1U) M_BOOT_RESET_REASON_PORZ:
(0x1U) M_BOOT_RESET_REASON_WARM:
(0x2U) M_BOOT_RESET_REASON_DEEPSLEEP:
(0x3U) M_BOOT_RESET_REASON_SOFT:
(0x4U) M_BOOT_RESET_REASON_STC_WARM:
(0x5U) M_BOOT_RESET_REASON_STC_PORZ:
(0x6U) |
[7:4] | SYS_RST_CAUSE[2:0] |
[15:7] | RADAR_WAKEUP_STATUS[7:0] |
[23:16] | RST_CAUSE[7:0] |