SWRU622A August   2024  – September 2024 AWRL1432 , AWRL6432 , IWRL1432 , IWRL6432 , IWRL6432AOP

 

  1.   1
  2.   Trademarks
  3. 1Introduction
  4. 2Basic Bootloader Flow
    1. 2.1 Programming Serial Data Flash Over UART (Bootloader Service)
    2. 2.2 Binary File Format
    3. 2.3 Flash Programming Sequence
    4. 2.4 Supported UART Commands/Response and Format
    5. 2.5 Flashing Sequence
    6. 2.6 ROM-Assisted Image Download Sequence
    7. 2.7 Booting Application Image
      1. 2.7.1 Booting From Serial Flash
      2. 2.7.2 Bootmode – SPI
      3. 2.7.3 Bootmode - UART
  5. 3Secondary Bootloader
    1. 3.1 SBL Execution Flow
      1. 3.1.1 Flash Memory Partitioning for SBL Execution
      2. 3.1.2 SBL Feature Modifications
      3. 3.1.3 SBL Development Considerations
  6. 4Warm Reset
    1. 4.1 Integrity Verification
    2. 4.2 LSTC/PBIST
    3. 4.3 Watchdog Timer
    4. 4.4 Reset-Triggered Flash Reload of Application
      1. 4.4.1 Hardware Solutions
        1. 4.4.1.1 PMIC I2C Messaging
        2. 4.4.1.2 External Watchdog Timer
        3. 4.4.1.3 External Voltage Monitoring or Voltage Supervisors
      2. 4.4.2 Software Solutions
        1. 4.4.2.1 Setting Boot Vector to 0x0
  7. 5Relevant Registers
    1. 5.1 Reset Registers
    2. 5.2 PC Registers
      1. 5.2.1 Addresses
  8. 6Revision History

2.6 ROM-Assisted Image Download Sequence

The ROM-assisted image download sequence is entered by placing the device in flashing mode. See Programming Serial Data Flash Over UART (Bootloader Service), for further details on the handshake with an external host to receive the image. Figure 2-2 shows the communication with the serial data flash (SDF).

ROM-Assisted Image Download SequenceFigure 2-2 ROM-Assisted Image Download Sequence

Key points:

  • The ROM-assisted download should work with all flash variants that allow for memory-mapped mode and Page program command (0x2), with one dummy byte and 24-bit addressing.
  • Setting the QE bit varies from one SDF vendor to another. The ROM bootloader supports setting the QE bit for Spansion® and Macronix® variants (certain specific part variants only) in this flow.
  • In addition to a checksum-based integrity check for every packet received over the UART, a CRC32-based integrity check is performed over the complete image. The CRC32 is computed incrementally as the packets are received and written to the SDF.