SWRU622A August   2024  – September 2024 AWRL1432 , AWRL6432 , IWRL1432 , IWRL6432 , IWRL6432AOP

 

  1.   1
  2.   Trademarks
  3. 1Introduction
  4. 2Basic Bootloader Flow
    1. 2.1 Programming Serial Data Flash Over UART (Bootloader Service)
    2. 2.2 Binary File Format
    3. 2.3 Flash Programming Sequence
    4. 2.4 Supported UART Commands/Response and Format
    5. 2.5 Flashing Sequence
    6. 2.6 ROM-Assisted Image Download Sequence
    7. 2.7 Booting Application Image
      1. 2.7.1 Booting From Serial Flash
      2. 2.7.2 Bootmode – SPI
      3. 2.7.3 Bootmode - UART
  5. 3Secondary Bootloader
    1. 3.1 SBL Execution Flow
      1. 3.1.1 Flash Memory Partitioning for SBL Execution
      2. 3.1.2 SBL Feature Modifications
      3. 3.1.3 SBL Development Considerations
  6. 4Warm Reset
    1. 4.1 Integrity Verification
    2. 4.2 LSTC/PBIST
    3. 4.3 Watchdog Timer
    4. 4.4 Reset-Triggered Flash Reload of Application
      1. 4.4.1 Hardware Solutions
        1. 4.4.1.1 PMIC I2C Messaging
        2. 4.4.1.2 External Watchdog Timer
        3. 4.4.1.3 External Voltage Monitoring or Voltage Supervisors
      2. 4.4.2 Software Solutions
        1. 4.4.2.1 Setting Boot Vector to 0x0
  7. 5Relevant Registers
    1. 5.1 Reset Registers
    2. 5.2 PC Registers
      1. 5.2.1 Addresses
  8. 6Revision History

4.4.2.1 Setting Boot Vector to 0x0

A software-based workaround to load the image from Flash is possible by modifying the jump address used in the warm reset flow. Proper care must also be taken to ensure that the FECSS (Front End Controller Subsystem) is in the correct state. A user must perform any necessary safety assessment of their own system to determine if this software-based workaround meets their needs. The flow of the workaround sequence is as follows:

Software Load From Flash on a Warm Reset Figure 4-2 Software Load From Flash on a Warm Reset
  1. Gracefully power down FECSS and HWASS
  2. Power on FECSS
  3. Write Boot vector to TOP_PRCM:PC_REGISTER2[24:0] = 0
  4. Write boot vector parity to TOP_PRCM:PC_REGISTER1[15:12] = 0
  5. Disable image integrity check - TOP_PRCM:PC_REGISTER1[5:3] = 0
  6. Disable STC test - TOP_PRCM:PC_REGISTER1[8:6] = 0
  7. Trigger warm reset - TOP_PRCM:RST_SOFT_RESET[0] = 1

Execution re-enters the RBL after the warm reset in step 7 occurs, which starts execution as shown in Figure 2-1. The RBL determines the reset reason as invalid because the reset registers have been cleared. It assumes a POR because of this, and the application image is loaded from Flash once again. The application or SBL can continue as designed, until another reset occurs.

View the watchdog_reset example in the MMWAVE-L-SDK under: <SDK-Install-Directory>/examples/drivers/watchdog/watchdog_reset/ for the fully-coded sequence to perform the reload from flash.