SWRU622A August   2024  – September 2024 AWRL1432 , AWRL6432 , IWRL1432 , IWRL6432 , IWRL6432AOP

 

  1.   1
  2.   Trademarks
  3. 1Introduction
  4. 2Basic Bootloader Flow
    1. 2.1 Programming Serial Data Flash Over UART (Bootloader Service)
    2. 2.2 Binary File Format
    3. 2.3 Flash Programming Sequence
    4. 2.4 Supported UART Commands/Response and Format
    5. 2.5 Flashing Sequence
    6. 2.6 ROM-Assisted Image Download Sequence
    7. 2.7 Booting Application Image
      1. 2.7.1 Booting From Serial Flash
      2. 2.7.2 Bootmode – SPI
      3. 2.7.3 Bootmode - UART
  5. 3Secondary Bootloader
    1. 3.1 SBL Execution Flow
      1. 3.1.1 Flash Memory Partitioning for SBL Execution
      2. 3.1.2 SBL Feature Modifications
      3. 3.1.3 SBL Development Considerations
  6. 4Warm Reset
    1. 4.1 Integrity Verification
    2. 4.2 LSTC/PBIST
    3. 4.3 Watchdog Timer
    4. 4.4 Reset-Triggered Flash Reload of Application
      1. 4.4.1 Hardware Solutions
        1. 4.4.1.1 PMIC I2C Messaging
        2. 4.4.1.2 External Watchdog Timer
        3. 4.4.1.3 External Voltage Monitoring or Voltage Supervisors
      2. 4.4.2 Software Solutions
        1. 4.4.2.1 Setting Boot Vector to 0x0
  7. 5Relevant Registers
    1. 5.1 Reset Registers
    2. 5.2 PC Registers
      1. 5.2.1 Addresses
  8. 6Revision History

5.1 Reset Registers

The reset registers can be used to identify if the type of reset that was triggered matches the intended reset the user wanted to trigger. Please see the tables below for descriptions of these registers and what the values in those register represent.

Table 5-1 SYS_RST_CAUSE Register
wWRLx432:TOP_PRCM:SYS_RST_CAUSE Filed Name Description
Bit#16 SYS_RST_CAUSE_SYS_RST_CAUSE_CLR

Clear's the sys_rst_cause register

0x0 -> sys_rst_cause capture enable

0x1 -> sys_rst_cause reg clear and disable
Bit#<2:0> SYS_RST_CAUSE_SYS_RST_CAUSE

System Reset Cause register

3'b001 - POR reset

3'b010 - Warm reset due to soft register

3'b100 - Warm reset due to wdog
Note: On a STC_POR reset, the SYS_RST_CAUSE register will be 0x0. This field will only be set to 3'b001 on the true POR reset.
Table 5-2 RADAR_WAKEUP_STATUS Register Field Descriptions
Bit Field Type Reset Description
31-21 RESERVED R/W X
20 radar_state_is_deep_sleep R 0h RADAR power FSM is in DEEP_SLEEP state
19 radar_state_is_go_to_deep_sleep R 0h RADAR power FSM is in GO_TO_DEEP_SLEEP state
18 radar_state_is_sleep R 0h RADAR power FSM is in SLEEP state
17 radar_state_is_idle R 0h RADAR power FSM is in IDLE state
16 radar_state_is_wake_up R 0h RADAR power FSM is in WAKEUP state
15-9 RESERVED R/W X
8 wakeup_status_clear R/W 0h Clear's the wakeup status and source register 0x
0 -> Wakeup status and source capture enable 0x
1 -> Wakeup status and source reg clear and disable
7-2 wakeup_source R 0h It indicate wakeup source from SLEEP/DEEP SLEEP state Bit
0 -> Sleep counter as Wakeup source Bit
1 -> UART as Wakeup source Bit
2 -> SPI as Wakeup source Bit
3 -> GPIO as Wakeup source Bit
4 -> RTC counter as Wakeup source Bit
5 -> FRC frame start intr as Wakeup source
1-0 wakeup_status R 0h It indicates the wakeup status of the device, whether it is Wakeup due to POR or from SLEEP/DEEP SLEEP state 0x
1 -> Wakeup from SLEEP 0x
2 -> Wakeup from DEEP SLEEP
Table 5-3 RST_CAUSE Register Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R X
7-0 COMMON R 3h Reset cause register for APP CPU
0x00 - All cleared
0x01 - Power On Reset (PoR)
0x02 - Subsystem Reset (Combination of Warm Reset initiated from PRCM using xWRLx432:TOP_PRCM:RST_APP_PD_SOFT_RESET and PoR reset)
0x04 - STC RESET
0x08 - Reserved
0x10 - CPU Only Reset triggered by writing to xWRLx432:APP_RCM:RST_FSM_TRIG<RST_FSM_TRIG_CPU>
0x20 - Core Reset initiated from PRCM using xWRLx432:TOP_PRCM:RST_SOFT_APP_CORE_SYSRESET_REQ (reset CPU unconditionally - by debugger) or xWRLx432:TOP_PRCM:APP_CORE_SYSRESET_PARAM_WAKEUP_OUT_STATE
0x40 - Reserved
Bit Source
[3:0] Reset Reason Identification by bootloader
M_BOOT_RESET_REASON_PORZ: (0x1U)
M_BOOT_RESET_REASON_PORZ: (0x1U)
M_BOOT_RESET_REASON_WARM: (0x2U)
M_BOOT_RESET_REASON_DEEPSLEEP: (0x3U)
M_BOOT_RESET_REASON_SOFT: (0x4U)
M_BOOT_RESET_REASON_STC_WARM: (0x5U)
M_BOOT_RESET_REASON_STC_PORZ: (0x6U)
[7:4] SYS_RST_CAUSE[2:0]
[15:7] RADAR_WAKEUP_STATUS[7:0]
[23:16] RST_CAUSE[7:0]