Shared Memory Considerations
- The SBL example runs from shared
memory to avoid conflicting with any application code in the M4 RAM.
- When loading an application with the SBL, the application cannot store any text,
data, or read-only information in shared memory. For more information, see the
DIG#14 in the errata. However, examples using L3
memory in shared memory can still utilize shared memory.
General Development Considerations
- IWR devices require RAM1 memory
bank to be explicitly initialized due to EFUSE differences between IWR and AWR
devices
- IWR devices have ECC disabled by default, therefore requiring explicit
memory initialization
- It is good practice to initialize all the memory banks, but results in a
delay in boot time
- Can also be resolved by disabling the SYSTICK timer which was
causing unnecessary access to memory banks upon execution of the
ISR
- If executing a warm reset on an
application that was loaded by the SBL, please make sure the warm reset
considerations are executed by the SBL and the SBL triggers the warm reset
- Specifically required for watchdog resets in the application that
trigger a warm reset as it is an uncontrolled reset that may not handle
all the necessary steps for ensuring a successful warm reset upon exit
of the program