SWRU622A August   2024  – September 2024 AWRL1432 , AWRL6432 , IWRL1432 , IWRL6432 , IWRL6432AOP

 

  1.   1
  2.   Trademarks
  3. 1Introduction
  4. 2Basic Bootloader Flow
    1. 2.1 Programming Serial Data Flash Over UART (Bootloader Service)
    2. 2.2 Binary File Format
    3. 2.3 Flash Programming Sequence
    4. 2.4 Supported UART Commands/Response and Format
    5. 2.5 Flashing Sequence
    6. 2.6 ROM-Assisted Image Download Sequence
    7. 2.7 Booting Application Image
      1. 2.7.1 Booting From Serial Flash
      2. 2.7.2 Bootmode – SPI
      3. 2.7.3 Bootmode - UART
  5. 3Secondary Bootloader
    1. 3.1 SBL Execution Flow
      1. 3.1.1 Flash Memory Partitioning for SBL Execution
      2. 3.1.2 SBL Feature Modifications
      3. 3.1.3 SBL Development Considerations
  6. 4Warm Reset
    1. 4.1 Integrity Verification
    2. 4.2 LSTC/PBIST
    3. 4.3 Watchdog Timer
    4. 4.4 Reset-Triggered Flash Reload of Application
      1. 4.4.1 Hardware Solutions
        1. 4.4.1.1 PMIC I2C Messaging
        2. 4.4.1.2 External Watchdog Timer
        3. 4.4.1.3 External Voltage Monitoring or Voltage Supervisors
      2. 4.4.2 Software Solutions
        1. 4.4.2.1 Setting Boot Vector to 0x0
  7. 5Relevant Registers
    1. 5.1 Reset Registers
    2. 5.2 PC Registers
      1. 5.2.1 Addresses
  8. 6Revision History

4.1 Integrity Verification

The RBL performs an integrity verification step to ensure that an application has valid data. The RBL makes the following assumptions when performing the integrity check in the STC_WARM reset flow:

  • RBL reads the boot vector from TOP_PRCM:PC_REGISTER2[24:0] to determine the boot vector to jump to
  • RBL performs the integrity check for the APPSS image only
  • RBL computes the CRC of the APPSS image based on image length (starting from boot vector) field in TOP_PRCM:PC_REGISTER3[31:0] and compares it with the data integrity check field TOP_PRCM:PC_REGISTER4[31:0]. It is expected that the application populates this register
  • The parity of TOP_PRCM:PC_REGISTER3 and TOP_PRCM:PC_REGISTER4 is expected to be correctly populated in TOP_PRCM:PC_REGISTER1[23:20] and TOP_PRCM:PC_REGISTER2[19:16] by the application. For more information, see Section 5.2.