SWRU622A August   2024  – September 2024 AWRL1432 , AWRL6432 , IWRL1432 , IWRL6432 , IWRL6432AOP

 

  1.   1
  2.   Trademarks
  3. 1Introduction
  4. 2Basic Bootloader Flow
    1. 2.1 Programming Serial Data Flash Over UART (Bootloader Service)
    2. 2.2 Binary File Format
    3. 2.3 Flash Programming Sequence
    4. 2.4 Supported UART Commands/Response and Format
    5. 2.5 Flashing Sequence
    6. 2.6 ROM-Assisted Image Download Sequence
    7. 2.7 Booting Application Image
      1. 2.7.1 Booting From Serial Flash
      2. 2.7.2 Bootmode – SPI
      3. 2.7.3 Bootmode - UART
  5. 3Secondary Bootloader
    1. 3.1 SBL Execution Flow
      1. 3.1.1 Flash Memory Partitioning for SBL Execution
      2. 3.1.2 SBL Feature Modifications
      3. 3.1.3 SBL Development Considerations
  6. 4Warm Reset
    1. 4.1 Integrity Verification
    2. 4.2 LSTC/PBIST
    3. 4.3 Watchdog Timer
    4. 4.4 Reset-Triggered Flash Reload of Application
      1. 4.4.1 Hardware Solutions
        1. 4.4.1.1 PMIC I2C Messaging
        2. 4.4.1.2 External Watchdog Timer
        3. 4.4.1.3 External Voltage Monitoring or Voltage Supervisors
      2. 4.4.2 Software Solutions
        1. 4.4.2.1 Setting Boot Vector to 0x0
  7. 5Relevant Registers
    1. 5.1 Reset Registers
    2. 5.2 PC Registers
      1. 5.2.1 Addresses
  8. 6Revision History

Booting From Serial Flash

In functional mode, the bootloading of an image from the SDF is the first bootmode attempted by the bootloader (see Figure 2-3). If for some reason quad or dual read mode fails in this process, the RBL tries single mode.

 Image Load Sequence Figure 2-3 Image Load Sequence

This bootmode involves the following steps (taken care of by the ROM Bootloader):

  1. Pinmux the QSPI pins of the xWRLx432 device.
  2. QSPI is set up to operate at (system clock / 2) = (160/2) = 80MHz.
  3. The SFLASH discoverable parameters (SFDP) command is issued to retrieve the JEDEC compliant response, which includes information regarding the SFLASH capabilities and command set. When the SFDP response is received, the information is used to communicate with the SDF and further interpret the contents and load the images.

Key points:

  • The ROM bootloader performs the read from the SDF, based on the highest capability mode (quad, dual, or single) as published by the SDF in response to the SFDP command.
  • For SDF variants that support quad mode, the quad mode commands are issued; if the quad enable (QE) bit is not set, the communication fails. In such cases, the load flow assumes that the QE bit in the SDF is already set.
  • Fallback images: the bootloader supports loading of images from the following locations as a fallback mechanism if one of the images is corrupted in the SDF. The locations of the images are:
    • META IMG1(SDF offset – 0x0)
    • META IMG2(SDF offset – 0x80000)
    • META IMG3(SDF offset – 0x100000)
    • META IMG4(SDF offset – 0x180000)

For image format details, see the AWRL6432, IWRL6432, AWRL1432, IWRL1432 Technical Reference Manual.