SWRZ072B May 2017 – December 2020 AWR1642
Asynchronous Assertion of SoC Warm Reset may not Work Reliably When Device Operating on PLL Clock
AWR1642 ES1.0
Asynchronous assertion of SoC warm reset through WARM_RESET pin, SW reset, watchdog reset, or Debug reset may not reliably work and may also result in a system hang scenario.
MSS VCLK must be switched from PLL clock to REFCLK by following the prescribed software sequence before a warm reset is issued.