SWRZ076D July   2018  – December 2020 CC1352P

 

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CPU_03

Arm® Errata #776924: VDIV or VSQRT instructions might not complete correctly when very short ISRs are used

Revisions Affected:

Revision E and earlier

Details:

On the Arm® Cortex®-M4F processor, the VDIV and VSQRT instructions take 14 cycles to execute. When an interrupt is taken a VDIV or VSQRT instruction is not terminated, and completes its execution while the interrupt stacking occurs. If lazy context save of floating point state is enabled then the automatic stacking of the floating point context does not occur until a floating point instruction is executed inside the interrupt service routine.

Lazy context save is enabled by default. When it is enabled, the minimum time for the first instruction in the interrupt service routine to start executing is 12 cycles. In certain timing conditions, and if there is only one or two instructions inside the interrupt service routine, then the VDIV or VSQRT instruction might not write its result to the register bank or to the FPSCR.

Conditions::

  • The floating point unit is present and enabled
  • Lazy context saving is not disabled
  • A VDIV or VSQRT is executed
  • The destination register for the VDIV or VSQRT is one of s0 - s15
  • An interrupt occurs and is taken.
  • The interrupt service routine being executed does not contain a floating point instruction.
  • An interrupt return is executed 14 cycles after the VDIV or VSQRT is executed.

    A minimum of 12 of these 14 cycles are utilized for the context state stacking, which leaves 2 cycles for instructions inside the interrupt service routine, or 2 wait states applied to the entire stacking sequence (which means that it is not a constant wait state for every access).

    In general this means that if the memory system inserts wait states for stack transactions then this erratum cannot be observed.

Implications:

The VDIV or VQSRT instruction does not complete correctly and the register bank and FPSCR are not updated, meaning that these registers hold incorrect, out of date, data.

For hand-written assembly code inside interrupt routines, this erratum should be considered.

Workarounds:

A workaround is only required if the floating point unit is present and enabled. A workaround is not required if the memory system inserts one or more wait states to every stack transaction.

When using TI-RTOS interrupts, all interrupt service routines will contain more than the 2 instructions and no workaround is required.

In all other cases, one of the following two workarounds must be implemented:

Workaround 1: Disable lazy context save of floating point state by clearing LSPEN to 0 (bit 30 of the FPCCR at address 0xE000EF34).

 

Workaround 2: Ensure that every interrupt service routine contains more than 2 instructions in addition to the exception return instruction.