SWRZ078C January   2018  – December 2020 CC1312R

 

  1.   1
  2.   2
  3.   3
    1.     4
    2.     5
    3.     6
  4.   7
    1.     8
    2.     9
    3.     10
    4.     11
    5.     12
    6.     13
    7.     14
    8.     15
    9.     16
    10.     17
    11.     18
    12.     19
    13.     20
    14.     21
    15.     22
    16.     23
    17.     24
    18.     25
    19.     26
    20.     27
  5.   28

CPU_Sys_01

The SysTick calibration value (register field CPU_SCS.STCR.TENMS) used to set up 10-ms periodic ticks is incorrect when the system CPU is running off divided down 48-MHz clock

Revisions Affected:

Revision E and earlier

Details:

When using the Arm® Cortex® SysTick timer, the TENMS register field (CPU_SCS.STCR.TENMS) will always shows the value corresponding to a 48-MHz CPU clock, regardless of the CPU division factor.

Workarounds:

One of the following two workarounds must be implemented:

Workaround 1: Do not use a divided down system CPU clock. In general, power savings are maximized by completing a task at full clock speed and then stopping the system CPU entirely after the task is complete.

 

Workaround 2: Read the system CPU division factor from the PRCM.CPUCLKDIV.RATIO register and compensate the TENMS field in software based on this value.

TI-provided drivers do not offer any functionality to divide the system CPU clock.