Revisions Affected:

Revision F and earlier

Details:

The ADC FIFO status flags do not behave correctly when the ADC FIFO is being read at the same clock cycle as a new sample is added.

Scenario A:

The EMPTY flag goes high even if there is one sample left in the ADC FIFO. This can happen if there is one sample in the ADC FIFO (the EMPTY flag is low), and this sample is being read on the same clock cycle as the ADC adds another sample. In this case, the EMPTY flag is incorrectly set high, and reading the ADC FIFO will cause an underflow even though the ADC FIFO is not empty. The only way to recover without a flush (AUX_ANAIF:ADCCTL.CMD = 3) is to add another sample (ADC or debug write).

Scenario B:

The ALMOST_FULL flag goes low when there are three samples in the ADC FIFO. This can happen if there are three samples in the ADC FIFO (the ALMOST_FULL flag is high), and one of the samples is being read on the same clock cycle as the ADC adds another sample. In this case, the ALMOST_FULL flag is incorrectly set low, even if there are still 3 new samples in the ADC FIFO.

Scenario C:

The FULL flag goes low while the ALMOST_FULL flag and OVERFLOW flag go high when there are four samples in the ADC FIFO. This can happen if there are four samples in the ADC FIFO (the FIFO_FULL flag is high) and one of the samples is being read on the same clock cycle as the ADC adds another sample. In this case, the FULL flag is incorrectly set low and the ALMOST_FULL flag and OVERFLOW flag are set high.

Workaround:

The CPU must use the ADC FIFO flags or corresponding events to know when to read the samples from the ADC FIFO.

The scenarios described will not occur if the CPU processing time from sample notification to completed ADC FIFO read is less than the ADC sampling period. Hence, once notified about available sample(s), the CPU should always read the ADC FIFO before starting other processing tasks. If the CPU processing time from sample notification to completed ADC FIFO read is longer than the ADC sampling period, the ADC FIFO will correctly overflow.

When using the Sensor Controller, you need to ensure that adcReadFifo() or adcPopFifo() is not called when an ADC conversion finishes. For most applications it makes sense to read the ADC FIFO before another sample is added to the FIFO, so that the FIFO never contains more than one sample, and only contains one sample for a short time.

In practice, this means:

• When using manual trigger: Call adcReadFifo() to empty the FIFO before or immediately after generating another manual trigger
• When using timer trigger: Call adcReadFifo() to empty the FIFO before or immediately after generating another timer trigger. As this is typically implemented with a loop (with one iteration per ADC sample), ensure that the worst-case loop iteration time is less than one ADC sample period.
• When using other triggers, which may or may not occur: Use adcGetFifoState() to poll the ADC FIFO state, and use adcPopFifo() to empty the FIFO as quickly as possible. Also, before disabling the ADC, ensure that no more triggers can occur (for example by disabling a GPIO input buffer) and wait until any ongoing ADC operation has finished.