Revision(s) Affected:

IWR6843AOP ES1.0 and IWR6843AOP ES2.0

Description:

While the device is halted in suspend mode by the debugger, the DMA is expected to complete the remaining transfers of a block, if the DEBUG MODE bit field of the GCTRL register is configured to '01'. Instead, the DMA does not complete the remaining transfers of a block but, rather stops after two more frames of data are transferred. Subsequent DMA requests from a peripheral to trigger the remaining frames of a block can be lost.

This issue occurs only in the following conditions:

• The device is suspended by a debugger
• A peripheral continues to generate requests while the device is suspended
• The DMA is setup to continue the current block transfer during suspend mode with the DEBUG MODE bit field of the GCTRL register set to '01'
• The request transfer type TTYPE bit in the CHCTRL registers is set to frame trigger ('0')

Workaround(s):

Workaround #1:

Use TTYPE = block transfer ('1'), when the DEBUG MODE bit field is '01' (finish current block transfer)

or

Workaround #2:

Use the DMA DEBUG MODE = '00' (ignore suspend), when using TTYPE = frame transfer ('0') to complete the block transfer, even after suspend/halt is asserted.