SWRZ092B April 2021 – March 2022 IWR6843AOP
Any EDMA Transfer That Spans ACCEL_MEM1 +ACCEL_MEM2 Memories of Hardware Accelerator May Result In Data Corruption Without Any Notification Of Error From The SoC
As per TPTC IP Spec, a Transfer request (TR) is supposed to access a single slave end point. ACCEL_MEM0/ACCEL_MEM1 memory banks of HWA are available via single slave point and ACCEL_MEM2/ ACCEL_MEM3 memory banks of HWA are available as another slave point (different from that of ACCEL_MEM0/ ACCEL_MEM1). Hence if a single TR is used to access a buffer spanning ACCEL_MEM1 and ACCEL_MEM2 memories of the HWA (i.e. a single buffer spanning 2 different slave points), the spec is not being adhered to. This errata is explicitly highlighting this spec requirement
Split the access into 2 TRs so that a single TR does not span ACCEL_MEM1 +ACCEL_MEM2. The 2 TRs can be chained.