SWRZ095A January   2020  – June 2022 CC2642R-Q1

PRODUCTION DATA  

  1.   Abstract
  2.   Trademarks
  3. 1Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support-Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Advisories
    1.     Power_03
    2.     PKA_01
    3.     PKA_02
    4.     I2C_01
    5.     I2S_01
    6.     CPU_01
    7.     CPU_02
    8.     CPU_03
    9.     CPU_Sys_01
    10.     Sys_01
    11.     Sys_03
    12.     SYSCTRL_01
    13.     SRAM_01
    14.     GPTM_01
    15.     ADC_01
    16.     ADC_02
    17.     ADC_03
    18.     ADC_04
    19.     ADC_05
  6. 4Revision History

GPTM_01

An Incorrect Value Might Be Written to the General-Purpose (GP) Timers MMRs (Memory Mapped Registers) When Simultaneously Accessing the PKA (Public Key Accelerator) Engine and/or the AES (Advanced Encryption Standard) Engine from a Different Controller

Revisions Affected:

Revision F and earlier

Details:

When writing data to the GP Timer MMRs from one controller while simultaneously accessing the PKA/AES modules from another controller (read/write), an incorrect value might be captured in the GP Timer MMRs. In some cases, the incorrect value is replaced by the correct one after two clock cycles, but not always. No issue is seen when accessing the modules from the same controller.

Workaround 1:

Avoid accesses to PKA/AES by other controllers while writing to the GP Timer MMRs. This can be accomplished by acquiring the relevant semaphores (depending on drivers/stacks) before writing to the GP Timer.

Note that the BLE stack executes crypto operations from ISR context. Other software must release the semaphores from a higher-priority ISR to avoid deadlocks.

Workaround 2:

Verify the value written to the GP Timer MMR by reading it back in software. Correct the value if necessary.