SWRZ095A January   2020  – June 2022 CC2642R-Q1

PRODUCTION DATA  

  1.   Abstract
  2.   Trademarks
  3. 1Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support-Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Advisories
    1.     Power_03
    2.     PKA_01
    3.     PKA_02
    4.     I2C_01
    5.     I2S_01
    6.     CPU_01
    7.     CPU_02
    8.     CPU_03
    9.     CPU_Sys_01
    10.     Sys_01
    11.     Sys_03
    12.     SYSCTRL_01
    13.     SRAM_01
    14.     GPTM_01
    15.     ADC_01
    16.     ADC_02
    17.     ADC_03
    18.     ADC_04
    19.     ADC_05
  6. 4Revision History

I2C_01

I2C Module Controller Status Bit is Set Late

Revisions Affected:

Revision F and earlier

Details:

The I2C.MSTAT[0] bit is not set immediately after writing to the I2C.MCTRL register. This can lead an I2C controller to believe it is no longer busy and continuing to write data.

Workaround:

Add four NOPs between writing to the MCTRL register and polling the MSTAT register.

The workaround is implemented in the TI-provided I2C Controller driver (I2CCC26XX.c) and in the I2C driver Library APIs (driverlib/i2c.c).

The workaround is available in all Software Development Kit (SDK) versions.