SWRZ101B December 2021 – December 2023 AM2732 , AM2732-Q1
PLL: Recommended PLL configuration if locked below 1GHz
If PLL is locked to less than 1 GHz following settings should be used to achieve low jitter clock out from PLL.
Recommendation for Sigma Delta settings
SD divider should be programmed to 0x4 [ MSS_TOPRCM:PLL_CORE_FRACDIVPLL_CORE_FRACDIV_REGSD]
Recommendation for PLL CTRL settings
SELFFREQDCO field should be programmed to 0x2 [MSS_TOPRCM:PLL_CORE_CLKCTRLPLL_CORE_CLKCTRL]