SWRZ101B December 2021 – December 2023 AM2732 , AM2732-Q1
CPSW: Ethernet Packet corruption occurs if CPDMA fetches a packet which spans across memory banks
Each memory bank in SoC has a separate memory controller. Even though memory addresses are contiguous, each bank is a separate entity with a separate controller.
If a memory bank received a memory request say 32 bytes and address of memory request is 16 bytes before end of memory bank, the behavior of the memory controller will be:
When the memory controller encounters end of memory bank after 16 bytes it will wrap around and give 16 bytes from the start of the memory bank.
This results in the packet corruption.
Ensure from application side single ethernet packet does not span across memory banks.