SWRZ101B December 2021 – December 2023 AM2732 , AM2732-Q1
Recommended HWA memInit Sequence
A race condition exists in the H/W : When the S/W clears a Done status bit , if in the same cycle H/W tries to set a different Done status bit, the later Done status bit is not latched by the register and is missed causing the S/W to hang.
The S/W shall wait for all the Done status bits (MEM_INIT_DONE[13:14]) to be set before attempting to clear the status (MEM_INIT_DONE[13:14])
Or
Attempt to perform Memint sequentially one after another.
Or
After starting memInit poll for the (MEM_INIT_STATUS[13:14] bits to go low, then only clear the status (MEM_INIT_DONE[13:14]) .