SWRZ101B December   2021  – December 2023 AM2732 , AM2732-Q1

 

  1.   1
  2.   Abstract
  3. 1Silicon Usage Notes and Advisories Matrices
    1.     Devices Supported
  4. 2 Usage Notes and Advisories
    1.     Silicon Usage Notes
      1.      i2293
      2.      i2295
      3.      i2300
      4.      i2324
      5.      i2364
      6.      i2389
      7.      i2390
    2.     Silicon Advisories
      1.      i2162
      2.      i2288
      3.      i2289
      4.      i2294
      5.      i2297
      6.      i2298
      7.      i2299
      8.      i2301
      9.      i2302
      10.      i2309
      11.      i2315
      12.      i2318
      13.      i2329
      14.      i2336
      15.      i2337
      16.      i2338
      17.      i2339
      18.      i2340
      19.      i2341
      20.      i2342
      21.      i2344
      22.      i2345
      23.      i2387
      24.      i2392
      25.      i2394
      26.      i2386
  5.   Trademarks
  6. 3Revision History

i2336

MiBSPI: MibSPI in Peripheral Mode in 3- or 4-Pin Communication Transmits Data Incorrectly for Slow SPICLK Frequencies and for Clock Phase = 1

Details:

The MibSPI module, when configured in multibuffered peripheral mode with 3-functional pins (CLK, SIMO, SOMI) or 4-functional pins (CLK, SIMO, SOMI, nENA), could transmit incorrect data when all the following conditions are met:

  • MibSPI module is configured in multibuffered mode
  • Module is configured to be a peripheral in the SPI communication
  • SPI communication is configured to be in 3-pin mode or 4-pin mode with nENA
  • Clock phase for SPICLK is 1
  • SPICLK frequency is MSS_VCLK frequency / 12 or slower

Workaround(s):

The issue can be avoided by setting the CSHOLD bit in the control field of the TX RAM (Multi-Buffer RAM Transmit Data Register). The nCS is not used as a functional signal in this communication; hence, setting the CSHOLD bit does not cause any other effect on the SPI communication.