SWRZ111A November   2021  – January 2022 CC2652P7

 

  1.   Trademarks
  2. 1Advisories Matrix
  3. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support-Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  4. 3Advisories
    1.     Radio_01
    2.     Radio_02
    3.     Power_03
    4.     PKA_01
    5.     PKA_02
    6.     I2C_01
    7.     I2S_01
    8.     CPU_01
    9.     CPU_02
    10.     CPU_03
    11.     CPU_Sys_01
    12.     Sys_01
    13. 3.1 Sys_05
    14.     SYSCTRL_01
    15.     IOC_01
    16.     ADC_01
    17.     ADC_02
    18.     ADC_03
  5. 4Revision History

Radio_02

High-Power PA Operation at Temperatures Below -20°C May Affect the 32-kHz Crystal Oscillator

Revisions Affected:

Revision B

Details:

When using the high-power PA at temperatures below -20°C and high output power, the PA may affect the 32-kHz crystal oscillator due to RF load impedance mismatch. In this situation the crystal oscillator will stop, and provided the clock loss detector is enabled (OSC_DIG:CTL0.CLK_LOSS_EN = 1), the device will reset. Antenna impedances outside of VSWR of 2:1 must be avoided in all operating scenarios.

Workaround:

  • For applications operating below -20°C, it is of particular importance to accurately follow the reference design for the RF balun and -matching network with respect to component values and layout. Amplitude- and phase balance through the balun must be <1dB and <6 degrees, respectively.
  • For PCB designs not adhering to the TI recommended guidelines or in applications where antenna impedance is subject to change due to external factors, output power should be limited to 17 dBm maximum.
  • Make sure the clock loss detector is enabled, OSC_DIG:CTL0.CLK_LOSS_EN = 1, to properly reset the device should the crystal oscillator be stopped.