SWRZ115B March 2021 – May 2024 AWR1843AOP
| Advisory Number | Advisory Title | AWR1843AOP |
|---|---|---|
| Main Subsystem | ||
| MSS#03 | Incorrect Handling of “Saturation” in FFT Hardware Accelerator’s Input / Output Formatter and Statistics Block | X |
| MSS#04A | Number of Samples (SRCACNT) Should be >3 for Correct Operation of FFT Hardware Accelerator | X |
| MSS#05A | Incorrect FFT Intermediate Stage Clip Status Indication | X |
| MSS#13 | Incorrect Read from FFT Hardware Accelerator After Complex Multiplication Operation | X |
| MSS#17 | Invalid Pre-fetch from MSS CR4 Processor (due to Speculative Read Operation from Tightly Coupled Memory Instance) Leads to Generation of MSS_ESM Group 3 Channel 7: MSS_TCMA_FATAL_ERR | X |
| MSS#18 | Core Compare Module (CCM-R4F) may Cause nERROR Toggle After First Reset De-assertion Subsequent to Power Application | X |
| MSS#19 | DMA Read from Unimplemented Address Space may Result in DMA Hang Scenario | X |
| MSS#20 | Radar Frame Stuck due to Missing Synchronizer Logic in Hardware | X |
| MSS#21A | Issue with HWA Input Formatter 16 bit Real Signed Format | X |
| MSS#22 | CAN-FD: Message Transmitted With Wrong Arbitration and Control Fields | X |
| MSS#23 | HWA Read Registers Cannot be Read Reliably When the HWA is Executing a ParamSet Instruction | X |
| MSS#24 | Limitation With Peak Grouping Feature in Hardware Accelerator | X |
| MSS#25 | Debugger May Display Unpredictable Data in the Memory Browser Window if a System Reset Occurs | X |
| MSS#26 | DMA Requests Lost During Suspend Mode | X |
| MSS#27 | MibSPI in Peripheral Mode in 3- or 4-Pin Communication Transmits Data Incorrectly for Slow SPICLK Frequencies and for Clock Phase = 1 | X |
| MSS#28 | A Data Length Error is Generated Repeatedly in Peripheral Mode When IO Loopback is Enabled | X |
| MSS#29 | Spurious RX DMA REQ From a Peripheral Mode MibSPI | X |
| MSS#30 | MibSPI RX RAM RXEMPTY Bit Does Not Get Cleared After Reading | X |
| MSS#31 | CPU Abort Generated on a Write to Implemented CRC Space After a Write to Unimplemented CRC Space | X |
| MSS#32 | DMMGLBCTRL BUSY Flag Not Set When DMM Starts Receiving A Packet | X |
| MSS#33 | MibSPI RAM ECC is Not Read Correctly in DIAG Mode | X |
| MSS#34 | HS Device Does Not Reboot Successfully on Warm Reset Getting Triggered by Watchdog Expiry | X |
| MSS#35 | EDMA TPTC Generates an Incorrect Address on the Read Interface, Causing one or More Data Integrity Failures, Hangs, or Extra Reads | X |
| MSS#37B | DCC Module Frequency Comparison can Report Erroneous Results | X |
| MSS#38A | GPIO Glitch During Power-Up | X |
| MSS#39 | The state of the MSS DMA is left pending and uncleared on any DMA MPU fault | X |
| MSS#40 | Any EDMA Transfer That Spans ACCEL_MEM1 +ACCEL_MEM2 Memories of Hardware Accelerator May Result In Data Corruption Without Any Notification Of Error From The SoC | X |
| MSS#42 | DSP L2 memory initialisation can reoccur on execution DSP self test (STC) OR DSP Power cycling execution by application. | X |
| MSS#43A | Read-data from internal registers of PCR is not reliable. Shared PCS region protection is also not supported | X |
| MSS#44 | SYNC IN input pulse wider than 4usec can cause a FRC lockstep error | X |
| MSS#45 | Bootup failure during the serial flash busy state | X |
| Analog / Millimeter Wave | ||
| ANA#08A | Doppler Spur Observed at Certain RF Frequencies | X |
| ANA#09A | Synthesizer Frequency Nonlinearity around 76.8 GHz when Synthesizer (Chirp) Frequency Monitor Enabled | X |
| ANA#10 | Unreliable Readings from Synthesizer Supply Voltage Monitor | X |
| ANA#11A | TX, RX Gain Calibrations Sensitive to Large External Interference | X |
| ANA#12A | Second Harmonic (HD2) Present in the Receiver | X |
| ANA#13B | TX1 to TX3 Phase Mismatch Variation over Temperature is Double that of TX2/TX1 and TX3/TX2 Combinations | X |
| ANA#15 | Excessive TX-RX Coupling or Reflection can Lead to Saturated RX Output | X |
| ANA#16 | LVDS Coupling to Clock System | X |
| ANA#17A | On-Board Supply Ringing Induced Spur | X |
| ANA#18B | Spurs Caused due to Digital Activity Coupling to XTAL | X |
| ANA#20 | Occasional Failures Observed During Calibration of the Radar Subsystem | X |
| ANA#21B | Out of Band Radiated Spectral Emission | X |
| ANA#22A | Overshoot and Undershoot During Inter-Chirp Idle Time | X |
| ANA#24A | 40-MHz OSC CLKOUT Causing Spurs in 2D-FFT Spectrum | X |
| ANA#27 | Digital Temperature Sensor Having Higher Error | X |
| Package | ||
| PACKAGE#02A | Surface Wave Artifact from PCB | X |