SWRZ115B March   2021  – May 2024 AWR1843AOP

 

  1.   1
  2. 1Introduction
  3. 2Device Nomenclature
  4. 3Device Markings
  5. 4Usage Notes
    1. 4.1 MSS: SPI Speed in 3-Wire Mode Usage Note
  6. 5Advisory to Silicon Variant / Revision Map
  7. 6Known Design Exceptions to Functional Specifications
    1.     MSS#03
    2.     MSS#04A
    3.     MSS#05A
    4.     MSS#13
    5.     MSS#17
    6.     MSS#18
    7.     MSS#19
    8.     MSS#20
    9.     MSS#21A
    10.     MSS#22
    11.     MSS#23
    12.     MSS#24
    13.     MSS#25
    14.     MSS#26
    15.     MSS#27
    16.     MSS#28
    17.     MSS#29
    18.     MSS#30
    19.     MSS#31
    20.     MSS#32
    21.     MSS#33
    22.     MSS#34
    23.     MSS#35
    24.     MSS#37B
    25.     MSS#38A
    26.     MSS#39
    27.     MSS#40
    28.     MSS#42
    29.     MSS#43A
    30.     MSS#44
    31.     MSS#45
    32.     ANA#08A
    33.     ANA#09A
    34.     ANA#10
    35.     ANA#11A
    36.     ANA#12A
    37.     ANA#13B
    38.     ANA#15
    39.     ANA#16
    40.     ANA#17A
    41.     ANA#18B
    42.     ANA#20
    43.     ANA#21B
    44.     ANA#22A
    45.     ANA#24A
    46.     ANA#27
    47.     PACKAGE#02A
  8. 7Trademarks
  9. 8Revision History

MSS#22

CAN-FD: Message Transmitted With Wrong Arbitration and Control Fields

Revision(s) Affected:

AWR1843AOP ES1.0

Description:

Under the following conditions a message with wrong ID, format, and DLC is transmitted:

  • M_CAN is in state "Receiver" (PSR.ACT = "10"), no pending transmission
  • A new transmission is requested before the 3rd bit of Intermission is reached
  • The CAN bus is sampled dominant at the third bit of Intermission which is treated as SoF (see ISO11898-1:2015 Section 10.4.2.2)

Under the conditions listed above it may happen, that:

  • The shift register is not loaded with ID, format, and DLC of the requested message
  • The M_CAN will start arbitration with wrong ID, format, and DLC on the next bit
  • In case the ID wins arbitration, a CAN message with valid CRC is transmitted
  • In case this message is acknowledged, the ID stored in the Tx Event FIFO is the ID of the requested Tx message and not the ID of the message transmitted on the CAN bus, no error is detected by the transmitting M_CAN

The erratum is limited to the case when M_CAN is in state "Receiver" (PSR.ACT = "10") with no pending transmission and a new transmission is requested before the 3rd bit of Intermission is reached and this 3rd bit of intermission is seen dominant.

When a transmission is requested by the CPU, the Tx Message Handler performs an internal arbitration and loads the pending transmit message with the highest priority into its output buffer and then sets the transmission request for the CAN Protocol Controller. The problem occurs only when the transmission request for the CAN Protocol Controller is activated between the sample points of the 2nd and 3rd bit of Intermission and if that 3rd bit of intermission is seen dominant.

This dominant level at the 3rd bit of Intermission may result from an external disturbance or may be transmitted by another node with a significantly faster clock.

In the described case it may happen that the shift register is not loaded with arbitration and control field of the message to be transmitted. The frame is transmitted with wrong ID, format, and DLC but with the data field of the requested message. The message is transmitted in correct CAN (FD) frame format with a valid CRC.

If the message loses arbitration or is disturbed by an error, it is retransmitted with correct arbitration and control fields.

Workaround(s):

Request a new transmission only if another transmission is already pending or when the M_CAN is not in state "Receiver" (when PSR.ACT ≠ "10").

Another option would be to add a checksum to the data field covering arbitration and control fields of the message to be transmitted.