SWRZ127A February   2022  – June 2022 CC2651R3SIPA

PRODUCTION DATA  

  1.   Abstract
  2.   Trademarks
  3. 1Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support-Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Advisories
    1.     Radio_04
    2.     Power_03
    3.     I2C_01
    4.     I2S_01
    5.     CPU_01
    6.     CPU_02
    7.     CPU_Sys_01
    8.     Sys_01
    9. 3.1 Sys_05
    10.     SYSCTRL_01
    11.     ADC_01
    12.     ADC_02
    13.     ADC_03
  6. 4Revision History

3.1 Sys_05

Elevated power-on-reset (POR) threshold voltage at low temperatures

Revisions Affected

Revision B

Details

When powering up the device from 0 V at temperatures < 0°C, the power-on-reset (POR) circuit may not release reset until VDDS reaches 2.3 V, and not at 1.8 V as intended. After POR has released the reset, an affected device will continue to operate at voltages down to 1.8 V.

This behavior is only observed during power up and does not occur when the device is subjected to an external pin reset, wake-up from shutdown, or watchdog reset.

The occurrence is rare and is only observed on very few devices.

Workaround

Workaround 1: Power-up the devices at VDDS > 2.3 V when operating at temperatures below 0°C.

or

Workaround 2: Power-up the device at VDDS < 2.3 V, trigger the Reset-pin from a host MCU or external circuitry.

In addition, when operating the device in external regulator mode, workaround 2 must be implemented. Please note that VDDS must not exceed 1.95 V in external regulator mode. This is applicable only to devices that have external regulator mode support.